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An operator view arranged from the most recently added article.
#001[memory]Memory Capacity Is Not Memory Bandwidth: RamRyder Gives Cloud VMs Their Own Channels#002[ai-infra]Fast Tokens, Slow Agents: Agentix Schedules the Program Behind Each LLM Call#003[fabric]Keeping Old NICs on the RDMA Path: What ByteDance's BURST Really Accelerates#004[ai-infra]Balanced Load, Unbalanced Latency: Alibaba Protects Quiet Storage Work from Bursts#005[ai-infra]The Same Context, Different Weights: DroidSpeak Reuses KV State Between Fine-Tuned Models#006[memory]Before the GPU Reads a Byte: FalconFS Moves the Directory Walk Off Training Clients#007[fabric]Azure Puts Stateful Networking Inside the Switch: The Deployment Logic of SONiC DASH#008[ai-infra]A New GPU Can Help Before the Model Finishes Loading: BlitzScale's Live Autoscaling#009[ai-infra]Inside the GPU Kernel: KPerfIR Makes Compiler Decisions Measurable#010[memory]Read Layout Is Not a Recovery Group: Okapi Separates Two Storage Decisions#011[ai-infra]The Bits That Never Change: IBP Compresses the PCIe Path Without Changing the Model#012[ai-infra]One Batch, Different Deadlines: AdaServe Builds a Speculation Tree for Each SLO#013[arch]Prefill Has Compute, Decode Has Bandwidth: POD-Attention Puts Both on the Same SM#014[ai-infra]Training Already Sends the Gradients: FlowCheck Rebuilds Checkpoints from Mirrored Traffic#015[ai-infra]Inference Owns the Deadline, Fine-Tuning Uses the Gaps: FlexLLM Schedules Tokens Together#016[ai-infra]Cloud Isolation Without Leaving the Fast Path: What Vela Learned at 1,500 GPUs#017[ai-infra]A Checkpoint Should Outlive the GPU Layout: ByteCheckpoint Saves Logical Tensors#018[fabric]The Fast Link Is Not the Only Link: MPCCS Stripes GPU Collectives Across Two Fabrics#019[ai-infra]The GPU Is Busy, but Training Is Slow: EROICA Finds the Faulty Step Online#020[ai-infra]Inference Can Borrow the Whole GPU: SIRIUS Makes Training Return Memory in Milliseconds#021[ai-infra]Long Contexts Leave GPU Waves Half Empty: LeanAttention Rebalances Decode#022[ai-infra]Stop Treating the Network as a Barrier: Mercury Compiles Remote HBM into the Operator#023[ai-infra]A Million Cores Do Not Behave Like One GPU: WaferLLM Rewrites Inference for the Mesh#024[ai-infra]Millions of Valid Configurations, One Deployment That Meets the SLO#025[ai-infra]When Remote HBM Becomes a Compiler-Managed Memory Level#026[news]Three Chips, Three Power Budgets: Intel’s Agentic AI Portfolio Test#027[news]Arm Stops at the Rack: What Its First Production CPU Changes#028[news]Ethernet Inside the Scale-Up Domain: The System Bet Behind Maia 200#029[news]The 72-GPU Rack Is the Product: How MI455X Becomes AMD Helios#030[news]Three Wafers Become One Service Unit: Reading Cerebras CS-4 Beyond Token Speed#031[news]One Core, Two Instruction Worlds: Why IBM Is Bringing Arm Inside the Mainframe#032[news]The Memory Controller Changes Sides: What NVHBM Really Buys#033[ai-infra]One TPU Generation, Two Networks: Why Google Split Training from Reasoning#034[arch]Not a Smaller GPU: How Jalapeño Rebuilds Inference Around Locality#035[snapshot]Batch Analytics Is Idle Even When Its CPU Is Allocated#036[snapshot]A Flat Profile Can Make a Faster Program Look Slower#037[snapshot]Serve Linearizable Reads from the Node the Client Needs#038[snapshot]An Exabyte Data Lake Can Feed LLM Training If It Learns the Schedule#039[snapshot]Unify Logs, Metrics, and Traces Without an In-Memory Fleet#040[snapshot]Long-Lived VMs Leave Placement Debt Behind#041[snapshot]RL Training Needs a Scheduler Inside the Job#042[snapshot]An LLM Optimization Is a Production Change, Not a Suggestion#043[snapshot]Put Billion-Vector Search Back on Flash#044[snapshot]A Rack Power Budget Changes with Hardware Age#045[snapshot]Instruction-Level iOS Analysis Without Generating Executable Code#046[snapshot]Put the VM Observer Beside the VMM#047[snapshot]Split CPU and Memory Virtualization Across Worlds#048[snapshot]Verify the Allocator That Runs on Twelve Million Phones#049[snapshot]Separate Log Durability from Log Order#050[snapshot]Datacenter Memory Reclamation Reverses the Cache Problem#051[snapshot]Follow the User Interaction Across Android Processes#052[snapshot]Memory Tiering Cannot Reclaim a Cold Object Trapped on a Hot Page#053[snapshot]One Fault-Domain Buffer Can Carry Fleet Maintenance#054[snapshot]Clear Accelerator Demand Every Minute, Not Every Quarter#055[snapshot]Replay the GPU Step That Corrupted the Model#056[snapshot]Learn the Rollout Tail Before It Forms#057[snapshot]Make the S3 Model Precise Enough to Be the Specification#058[snapshot]Turn Kernel Constants into Millisecond Control Points#059[snapshot]Cloud Garbage Collection Can Punch Holes Before It Moves Bytes#060[snapshot]Container Startup Is a Metadata Path Before It Is a Download#061[snapshot]An SSD Failure Alert Must Explain the Combination That Fired#062[snapshot]Data Integrity Must Cross the Filesystem Boundary#063[snapshot]Database Compression Needs a Fast Path for the Bytes That Commit#064[snapshot]File Synchronization Can Reuse Work the Storage Layer Already Did#065[snapshot]Zoned Mobile Flash Works Only When Android Preserves Its Contract#066[snapshot]Memory-Safe Compartments Without an MMU#067[snapshot]Reuse Yesterday's Optimizer State for the Next Allocation Round#068[snapshot]Compress Keys, Values, Tokens, and Heads Differently#069[snapshot]One Output Token Changes the Inference Engine#070[snapshot]Freeze the RDMA Device, Not the Application Contract#071[snapshot]Let SmartNIC Control Tasks Borrow Data-Plane Cores#072[snapshot]One Publishing Path for Live and Collaborative Video#073[snapshot]When One Ordered Stream Must Reach Thousands of Readers#074[snapshot]A Failure Detector Fast Enough to Change the Protocol#075[snapshot]Recover the Reduction Tree from Floating-Point Outputs#076[snapshot]Record the Kernel Slice, Not the Entire Machine#077[snapshot]Spend Latency When the Shopper Stops Moving#078[snapshot]The Receive Ring Was Doing Two Jobs#079[snapshot]Move Paging Policy Out, Keep the Fault Path In#080[snapshot]One Training Contract Across Ten Million CPU Cores#081[snapshot]When an LLM Writes the Port and a Solver Repairs It#082[snapshot]A Sub-Millisecond Fork Does Not Make a Fast Function#083[snapshot]A Two-Second Freshness Contract Without Rebuilding the Cache#084[snapshot]Long Contexts Turn Equal Tokens into Unequal Work#085[snapshot]A Filesystem Process Can Crash Without Erasing the Application's Past#086[snapshot]A TEE Must Reject Disk States the Application Never Committed#087[snapshot]Container Startup Wants a Memory Image, Not a Storage Archive#088[arch]Implementation Details Became System Constraints: 35 Company-Affiliated Papers at MICRO 2025#089[arch]Production Evidence Replaced the Architecture Promise: 43 Company-Affiliated Papers at ISCA 2026#090[arch]Architecture Reached the Fleet: 43 Company-Affiliated Papers at ISCA 2025#091[arch]Scale Exposed the Hidden Architecture Bill: 28 Company-Affiliated Papers at HPCA 2026#092[arch]Measured Architecture Became an Operating Policy: 40 Company-Affiliated Papers at HPCA 2025#093[arch]AI Systems Turned Every Layer into a Scheduling Problem: 44 Company-Affiliated Papers at ASPLOS 2026#094[arch]The Hardware-Software Contract Moved Again: 59 Company-Affiliated Papers at ASPLOS 2025#095[memory]HBM Saves Clock Power by Rebuilding Four Phases at the Data Groups#096[silicon]What Commercial AI EDA Has Actually Put Through Tapeout#097[silicon]When AI Placement Becomes Production Silicon#098[arch]RTL Automation Starts After the First Draft#099[arch]AI Can Search a Microarchitecture, but It Still Needs an Executable Contract#100[silicon]Why AI Reached Industrial Physical Design Before Architecture#101[silicon]Place and Route Is Becoming an Objective Negotiation#102[silicon]The Next EDA Advantage Is a Recipe That Transfers#103[fabric]Pooling PCIe Devices Without a PCIe Switch#104[ai-infra]Alibaba Rebuilt Cloud RDMA Across Host, PCIe, and Fabric#105[fabric]An RDMA NIC Needs a Scheduler, Not Just Faster Queues#106[ai-infra]Why Elastic Tensors Help PCIe GPU Servers More#107[memory]RDMA Remote Memory Without a Memory-Node CPU#108[fabric]Routable PCIe Is a Fabric, Not a Longer Bus#109[arch]Making a SmartNIC Fast Across a Slow PCIe Boundary#110[fabric]The Protocol Debt Inside Hyperscale RoCE#111[silicon]The Soft Materials Set the Shape of the Advanced Package#112[silicon]Evatec Uses Film Stress to Flatten the Packaging Wafer#113[silicon]IBM Moves the Heat Spreader into the Organic Substrate#114[fabric]Count the Laser: Co-Designing a 224 Gb/s Coherent CPO Link#115[fabric]CPO Has to Survive Reflow: Intel's Fiber-to-EMIB Package#116[fabric]The 400 µm Modulator That Pushes CPO to 212 Gb/s per Wavelength#117[memory]No Giant Switch: How Octopus Builds a 96-Server CXL Memory Pod#118[memory]A Real CXL Memory Box Under SAP HANA: What Can Move, and What Must Stay Local#119[fabric]Pool the Buffer, Not the Device: A CXL Shortcut Around PCIe Switches#120[memory]Eighty Percent Far, Eighty-Five Percent Fast: A Database Placement Rule for CXL#121[fabric]One Photonic Switch, Two Routing Dimensions#122[silicon]At 100 GHz, the Laser Package Becomes Part of the Circuit#123[fabric]Let the Optical Topology Follow the GPU Allocation#124[ai-infra]The GPU Did Not Crash, Yet 1,024 Workers Slowed Down#125[ai-infra]When Idle Models Leave the GPU: Paying Only for Active Inference#126[fabric]One DPU, Eight RNICs: Tencent's Pegasus Network for Bare-Metal AI Cloud#127[silicon]Three Nanosheets over Three: Samsung Builds Logic Upward at 42 nm#128[fabric]Compile the Fabric before Deploying It: Meta's Matryoshka Network Design System#129[silicon]CFET Leaves the Device Lab: TSMC Runs an Oscillator and SRAM below 48 nm#130[fabric]One RoCE Fabric, Four Distance Classes: Meta's Communication Stack for 100K+ GPUs#131[fabric]UCIe Crosses the Rack in Light: Ayar Labs' 8.192 Tb/s Optical Retimer#132[fabric]Optics Moves Inside the Silicon: Celestial AI's Photonic Fabric Module#133[fabric]A 4,000 mm² Optical Backplane: Reading Lightmatter's Passage M1000#134[silicon]A 600 mm² Mainframe Die Becomes a System: Inside IBM Telum II#135[ai-infra]The Same H100 Is Not the Same Rental: Measuring the GPU Cloud Lottery#136[memory]KV Reuse Breaks When the Text Moves, Even If the Text Does Not#137[fabric]A Flow-Size Distribution Cannot Describe a Burst#138[fabric]A 100K-GPU Network Starts as a Compiler Problem#139[fabric]Spend Delay Before the First Hop to Buy Back Bandwidth#140[memory]The Fastest Model Loader Changed the Page Cache, Not the Framework#141[memory]Five Regions Changed the Economics of Apple's Object Store#142[memory]Compression Improves When the Filesystem Sorts Before It Packs#143[memory]The Boundary Learned to Move: 52 Industry Memory and Storage Papers in 2026#144[fabric]Beyond NVLink and Scale-Out Networks: A One-Chip-Like CXL Datacenter#145[silicon]Arrays, Timing, and Structured Compute: Industry Circuits in 2026#146[silicon]AmpereOne Hides Memory Tags in the Bits a Server Already Pays For#147[silicon]Li Auto Lets the Compiler Drive Data Instead of Rebuilding a GPU Cache#148[silicon]Microsoft's Rowhammer Defense Sleeps Until One Sub-Bank Looks Dangerous#149[ai-infra]Reasoning Models Hit the Memory-Capacity Wall Before the Compute Ceiling#150[arch]SPEC CPU 2026 Stops Pretending Every Core Runs the Same Program#151[memory]The SSD Stayed Local, but Its Control Path Moved Three Times#152[memory]A Thousand Cartridges, Four Drives: Why Tape Cloud Storage Must Wait on Purpose#153[ai-infra]Meta Gives Kernel Optimization a Search Tree and a Memory#154[memory]The Hierarchy Became the Product: 34 Industry Memory and Storage Papers from 2025#155[fabric]Ask the Switch Which Path the Probe Actually Took#156[silicon]Precision Moves Into the Architecture: Industry Circuits in 2025#157[fabric]A Local Queue Cannot See the Congestion Two Switches Away#158[fabric]The Training Job Already Knows Which Network Paths Matter#159[arch]A CPU Benchmark That Meta Was Willing to Buy Servers With#160[ai-infra]Why Llama 3 Needed Four Kinds of Parallelism at Once#161[ai-infra]Alibaba Makes Collective Communication Diagnose the Cluster#162[ai-infra]The Largest GPU Jobs Fail Most, but Small Jobs Still Set Fleet Policy#163[ai-infra]AI Energy Needs a Meter That Survives Nine Orders of Magnitude#164[silicon]What Industry Put on Silicon in 2024#165[memory]Memory Stopped Being a Component: 35 Industry Papers from 2024#166[silicon]MI300A Turns the Accelerator Package into the Compute Node#167[silicon]FuriosaAI Replaces the Fixed Matrix with a Shape-Shifting Tensor Engine#168[arch]Vera Rebalances the CPU: 88 Cores Fed by 1.2 TB/s#169[ai-infra]The Agent Graph Becomes the Cloud Scheduler: Murakkab Optimizes the Whole Workflow#170[memory]A Cache Hit That Arrives Late Is Still a Miss: Strata Schedules Long-Context Memory#171[ai-infra]Fill the Idle Half of On-Policy RL: Weave Co-Schedules Rollout and Training#172[ai-infra]When Storage Understands the Job: AITURBO Turns AI I/O into a Group Operation#173[ai-infra]The Datacenter Became the Runtime: Nine Industry Papers That Redefined AI Infrastructure#174[ai-infra]Idle Is Not Available: The Accounting Problem Inside Alibaba's 155,410-GPU Fleet#175[ai-infra]A Silent GPU Error Needs Three Different Questions#176[ai-infra]Trace the Request That Missed Its SLO, Not Every Request Around It#177[ai-infra]The Pipeline Is No Longer Made of Identical Bricks#178[ai-infra]Move the Training Job Before It Learns That a Machine Left#179[ai-infra]The Weather File Expires Before the Datacenter: Google Reprices Cooling for 2044#180[ai-infra]Power Is the Cluster: What 83,000 GB200s Teach About 150 MW#181[ai-infra]What a Neocloud Number Proves, and What It Leaves Unmeasured#182[fabric]An AI Fabric Needs Three Views of the Same Failure#183[ai-infra]When Thousands of GPUs Wait for Storage: Reading MLPerf Storage 2.0#184[arch]One Scheduler for Ten Accelerators: XSched's Three Levels of Preemption#185[ai-infra]Three Percent Globally, a Grid Problem Locally: Reading the IEA's AI Forecast#186[memory]Mobile Memory Takes the Server Socket: LPDDR6 Silicon, SOCAMM2 and DRAM That Computes#187[memory]NAND Moves Up a Tier: Reading the First High Bandwidth Flash Specification#188[silicon]The PCIe Tax on CXL, and the 4 nm Silicon Built to Repeal It#189[silicon]Dropping the PHY: d-Matrix Bonds Compute Directly onto DRAM#190[fabric]Who Wires the Rack: Reading UALink Against NVLink and Ethernet#191[ai-infra]Seven Models, One GPU: What the Long Tail Costs and How Aegaeon Reprices It#192[ai-infra]Evict First, Ask Questions Later: How ByteDance Keeps 9,600 GPUs Worth Training On#193[fabric]The FLOPS You Cannot Buy, You Wire: Inside Tencent's Half-Million-GPU Fabric#194[fabric]Firing the Switch: A Scale-Up Domain Built from Transceivers#195[ai-infra]The Hardware Wishlist DeepSeek Wrote on a Halved NVLink#196[silicon]No HBM, No Apologies: MTIA 2i and Meta's Productionization Ledger#197[ai-infra]One Controller Above, Many Below: HybridFlow, the Engine Inside verl#198[ai-infra]Buying Back FLOPs with DRAM: Mooncake, the Cache That Serves Kimi#199[memory]CXL Leaves the Lab: How Meta Turned Retired DDR4 into a Production Memory Tier#200[memory]KVCache Without the Network: Alibaba Runs LLM Serving on a Real CXL 2.0 Switch