The 2025 industry record did not converge on one universal memory. It did the opposite. Six ISSCC papers specialized LPDDR, GDDR, NAND, and STT-MRAM. Fifteen FAST papers changed the software path for GPU data, KV caches, metadata, DPUs, mobile storage, and heterogeneous devices. Thirteen ACM Transactions on Storage records extended storage from byte-addressable indexes to magnetic tape and glass archives. Together, the 34 records describe a hierarchy whose tiers have increasingly different physics and increasingly shared policy.

This index covers company-affiliated work in the main ISSCC external-memory session, regular FAST technical papers, and ACM TOS articles first published in 2025. Processor-local SRAM and compute-in-memory are handled by the annual circuit series. Keynotes, panels, introductions, surveys without a company author, and repeated journal versions are not counted twice. Mooncake has a dedicated Silicon & Systems review; it remains in this publication record but the analysis links to the existing article rather than creating another digest.

A conceptual storage and memory server shows DRAM, controllers, accelerators, and NVMe media while a deterministic overlay counts 34 company-affiliated ISSCC, FAST, and ACM TOS records from 2025. It is not a product photograph. Original figure created for this article.

LPDDR and GDDR spent circuit complexity to preserve system energy

Samsung’s 16 Gb LPDDR5 Ultra Pro reported 12.7 Gb/s per pin in a fifth-generation 10 nm DRAM process. Four-phase self-calibration and AC-coupled transceiver equalization addressed timing and channel loss instead of treating them as fixed platform margins. LPDDR’s appeal comes from lower energy and compact channels, but those advantages survive only if clock distribution, termination, calibration, and reliability do not require excessive guard bands.[1]

Samsung’s 24 Gb GDDR7 reached 42.5 Gb/s. Its design optimized the write-clock distribution and transmitter emphasis while reducing voltage and timing margin overhead. GDDR and LPDDR illustrate why a pin-rate comparison is incomplete. GDDR buys aggregate bandwidth over a board channel and accepts a larger power envelope. LPDDR targets energy-constrained systems and shorter channels. The memory controller, package, board, and workload determine which rate becomes useful bandwidth.

The strongest systems implication arrived in the ISSCC plenary rather than a product session: memory capacity, power, and bandwidth were already diverging into HBM, LPDDR-wide interfaces, SSD, and CXL tiers. The technical papers supplied the circuit evidence for that specialization. The system papers then showed the software price.

NAND added layers while controllers defended energy and throughput

Samsung reported a 4XX-layer 1 Tb TLC NAND at 28 Gb/mm² with 5.6 Gb/s-per-pin I/O. KIOXIA and Western Digital reported another 1 Tb TLC design with 29% better read-energy efficiency and 4.8 Gb/s I/O. SK hynix reported a 321-layer 2 Tb QLC device with 75 MB/s program throughput. Each result improved a different limiting resource: density, read energy, interface movement, or program parallelism.[1]

No single value ranks these devices. QLC stores more bits per cell but narrows voltage margins and raises controller work. More layers improve areal density but increase process and vertical-channel challenges. Higher pin speed moves data faster after it is available; it does not shorten every program or erase event. The 2025 papers therefore make sense only with a workload’s read-write mix, queue depth, endurance target, and background maintenance.

The 64 Gb DDR4-compatible STT-MRAM from KIOXIA and SK hynix made a different trade. A time-controlled discharge-reading scheme supported a 1T-1MTJ cross-point cell. The DDR4 interface provides a familiar system boundary, while nonvolatility changes retention, write behavior, and endurance. Compatibility can lower adoption cost, but it does not make the medium behave like DRAM.

GPU storage became a first-class path

GeminiFS treated the GPU as a filesystem participant rather than a passive consumer behind CPU staging. PolyStore combined capabilities across heterogeneous storage. HiDPU placed hybrid indexing on a DPU for disaggregated storage. HaSiS used hardware assistance for a shared analytical and transactional index. These FAST papers moved metadata and indexing toward the engines that consume data.[2]

Moving code closer to storage is not automatically beneficial. A GPU path must preserve isolation and filesystem semantics. A DPU index must be kept consistent with host state. A computational device may save PCIe traffic yet introduce a second execution and failure domain. The contribution is credible when the paper measures the complete path, including synchronization and fallback, rather than only the accelerated kernel.

Samsung’s DJFS showed another hardware-software contract. Directory-granularity journaling targeted CMM-H SSDs, which expose capabilities beyond a conventional block device. Samsung’s PolyStore participation and later journal extension likewise show that heterogeneous media need a common control layer. Device features become product value only after the filesystem can decide when to use them.

KV-cache storage turned inference into a data-management workload

Mooncake separated the KV cache of an LLM serving system from GPU computation and used distributed storage to trade capacity for recomputation. IMPRESS organized multi-tier prefix KV storage using estimated importance. A Huawei-affiliated billion-scale vector-search paper split filtering and reranking across CPU and GPU. These were storage papers because inference had become dominated by state placement and reuse.[2]

The central variable is not nominal storage bandwidth. It is whether a requested prefix or vector candidate arrives before the accelerator would finish recomputing it. A late hit is functionally a miss. Admission, prefetch, network scheduling, and eviction therefore need model-serving context. Our dedicated Mooncake review examines that architecture in depth; the annual index keeps it visible as part of the 2025 record without duplicating the article.

Cloud storage moved from one service to a family of control loops

NetApp’s Cloudscape study described how storage services appear inside modern cloud architectures. Huawei’s FlacIO changed container-image I/O, while Alibaba’s GogetaFS merged metadata management for deduplication. Ant Group’s AtomicDisk protected a virtual disk used by trusted execution environments. OPPO’s MedFS used metadata-enabled delta compression on mobile devices. The media ranged from cloud volumes to phones, but each paper added policy at a boundary where generic block I/O had lost information.[2]

The ACM TOS records make the operational direction explicit. Alibaba documented cloud-block-store evolution around performance, elasticity, availability, and hardware offload. Amazon participated in SquirrelFS, which uses Rust’s type system to help check crash consistency. Dell’s IDEA journal version carried deduplication indexing beyond its FAST paper. Huawei extended RDMA-attached memory with SSD and investigated a large-node B+ tree. The journal articles are valuable because they expose longer design arcs, not because a journal label makes every claim stronger.

Archives forced a different definition of performance

Microsoft’s Project Silica and related holographic-storage article studied glass for long-lived cloud archives. IBM researchers reviewed magnetic tape. DDN and Whamcloud reviewed Lustre’s evolution. Western Digital joined ZonesDB, a write-optimized key-value store for zoned storage. These records stretch the hierarchy from GPU-time-scale reuse to retention measured in years.[3]

At archival scale, throughput is only one cost. Media life, environmental control, migration frequency, robotic access, index durability, and the energy of keeping data readable can dominate. A glass or tape result should not be compared with flash latency. Its competing baseline is the total cost and risk of preserving cold data through several hardware generations.

Three decisions define the hierarchy

First, decide where data becomes authoritative. GPU memory, host DRAM, device cache, remote KV store, flash, disk, tape, and glass cannot all be the source of truth. Recovery and consistency depend on one declared authority and a tested transition between tiers.

Second, decide which latency is hidden and which is paid. Prefetch and tiering can overlap movement, but they do not erase it. An admission policy should report late hits, wasted transfers, and recomputation, not only hit rate.

Third, decide which resource is consumed to save another. QLC trades margin and controller work for density. Learned caching consumes model complexity to save device traffic. Hardware offload consumes another execution domain to save CPU time. Archives consume access latency to lower long-term cost. The right design names that exchange directly.

A hierarchy is only as good as its admission policy

The 2025 papers added tiers faster than they simplified decisions. KV caches could live in accelerator memory, host DRAM, remote DRAM, or storage. Container images could be cached as files, blocks, or decompressed layers. Heterogeneous devices could expose separate features through PolyStore or be hidden behind a common interface. Each option creates an admission problem: which object deserves the scarce, faster tier, and for how long?

Hit rate is an incomplete answer. A large object may create one hit but occupy enough space to evict many smaller reusable objects. A prefix KV cache may have a high reuse probability but arrive after recomputation would have finished. A container layer can be popular across nodes yet expensive to invalidate after an update. Admission therefore needs size, reuse distance, retrieval time, recomputation cost, and dependency criticality.

Eviction requires the same context. LRU can work when recent use predicts future use, but model serving and batch pipelines often have phase behavior known to the scheduler. Learned policies such as 3L-Cache and the mechanisms around Baleen’s earlier line of work can improve prediction, yet they need a safe response to distribution shift. A product should expose the baseline policy, decision confidence, and a way to disable or bound learning. Otherwise, a cache controller becomes an opaque source of tail latency.

Offload created a second operating system

GPU filesystems, DPUs, computational storage, and device-specific SSD features all move execution away from the host CPU. That can avoid data movement and free host cycles. It also creates another scheduler, allocator, protection boundary, and upgrade path. In effect, the storage system gains a second small operating system even when the paper calls it an accelerator.

The key questions are state ownership and failure recovery. If a DPU holds the authoritative index, how does the host recover it after a reset? If the GPU performs filesystem operations directly, where are permissions and durability ordering enforced? If a device function is upgraded independently, can old hosts interpret its metadata? HaSiS, HiDPU, GeminiFS, DJFS, and PolyStore each address part of this contract, but deployment requires the parts to meet at one boundary.

Isolation is equally important. Sharing a DPU or near-storage accelerator across tenants can create timing and capacity interference outside conventional CPU accounting. The system should report queue occupancy, memory use, and rejected work per tenant. Offload is valuable when it removes a measured bottleneck and keeps these controls visible. It is weaker when it only relocates CPU work to a device whose utilization is omitted from the result.

AI storage needs deadline-aware metrics

Traditional storage benchmarks emphasize IOPS, throughput, and latency distributions. AI serving adds deadlines that depend on computation. A KV block is useful only if retrieval finishes before the attention step needs it. Model weights are useful only if loading completes before an accelerator would otherwise remain idle. Training data is useful only if preprocessing and delivery keep the next batch ready.

Mooncake and IMPRESS make the deadline visible by connecting storage placement to recomputation and prefix value. GeminiFS and the CPU/GPU vector-search work connect the data path to accelerator execution. The next evaluation step is a joint timeline: compute active, compute stalled for data, storage busy on useful transfers, storage busy on wasted prefetch, and network blocked by competing traffic. Aggregate throughput can hide every one of these states.

Quality can also belong in the metric. A vector-search system may trade recall for filtering speed. A model-serving cache can affect scheduling fairness or time to first token. A compressed mobile filesystem can change energy and responsiveness differently. A complete claim pairs infrastructure efficiency with the task-level quality and service objective it preserves.

Persistent memory did not remove persistence software

STT-MRAM and nonvolatile memory can retain data without the refresh behavior of DRAM, but persistence is more than cells retaining bits. Applications need ordering, atomicity, version identity, and recovery after a crash. The LSM and B+ tree work, SquirrelFS, AtomicDisk, and hybrid-memory studies show that software still decides when a state becomes durable and how partial updates are interpreted.

The familiar interface of DDR4-compatible MRAM lowers one integration barrier while raising an architectural question. If software treats it exactly like volatile DRAM, it may ignore valuable persistence. If it treats every store as durable, it may pay unnecessary ordering and write costs. The memory controller and operating system need an explicit persistence model, including which buffers and caches are inside the protected domain.

Security adds another boundary. AtomicDisk protects a virtual disk against eviction attacks in a trusted-execution setting, but the encrypted or integrity-protected path must still cover rollback and metadata. Hardware isolation does not automatically make storage state fresh. A product claim should state the adversary, trusted components, persistence boundary, and recovery behavior together.

Archival storage needs a migration budget

Glass and tape target long life, but no archive is maintenance-free. Formats, readers, indexes, error-correction schemes, and service software evolve. Even a medium with excellent physical retention needs a migration plan before the surrounding hardware becomes unavailable. Project Silica and the magnetic-tape review are best read as system programs that include media, readers, robotics or access mechanisms, and catalog management.

A migration budget contains more than bytes divided by drive bandwidth. It includes read verification, retries, reconstruction, network movement, temporary duplicate capacity, and the operational risk of touching old media. The interval between migrations changes total cost. Too frequent wastes energy and hardware; too late increases unreadable or unsupported inventory.

This is why archive comparisons should report retained logical bytes, physical redundancy, expected repair traffic, retrieval service objective, reader availability, and power in idle and active states. Flash, disk, tape, and glass can each win under a different combination. The hierarchy needs an explicit data-lifecycle policy to select among them.

What a deployment review should demand

A deployment review can reduce the 2025 field to five tests. The first is an end-to-end boundary diagram showing processors, memories, devices, networks, software layers, and authoritative state. The second is a resource ledger covering capacity, bandwidth, CPU or offload cycles, device writes, and network bytes. The third is a time-series evaluation that includes warmup, workload phase changes, steady state, and recovery.

The fourth test is a failure matrix. It should cover host reset, device reset, network partition, corrupted metadata, partial upgrade, and loss of the policy engine. The fifth is an escape path. Specialized APIs, learned policies, and device offload should degrade to a correct mode that operators can understand. A mechanism that performs well only while every hint and accelerator is available is not a resilient hierarchy.

These tests also clarify what the 2025 public record did not yet settle. Long-running evidence for mixed HBM, LPDDR, CXL, and storage fleets remained limited. The interaction between AI cache policies and multi-tenant fairness needed broader study. Glass archives had promising system evidence but not a commodity deployment record comparable with tape. The papers establish mechanisms and measured points; they do not eliminate the need for workload-specific validation.

How the annual count was checked

The inventory was built from the official ISSCC advance program, the FAST technical-session page and linked paper records, and ACM TOS publication metadata. Company affiliations were taken from the published author lines, not inferred from acknowledgments or a later employer. A university-only paper was excluded even when a company funded or discussed similar work.

Conference and journal versions require care. IDEA appeared as a FAST paper in 2024 and as a TOS record in 2025. Mooncake appeared at FAST in 2025 and later as a journal extension. The publication index retains distinct records because readers may encounter both, but the editorial system creates one canonical deep review and labels extensions. This prevents inflated article counts while preserving the literature trail.

The cutoff rule matters most for online-first journals. A DOI assigned in 2025 can later enter a numbered issue. We use first public publication for the annual bucket and do not count the issue assignment again. Counts therefore describe an auditable public record, not a claim that every corporate research project or paywalled workshop presentation has been captured.

A comparison worksheet for specialized tiers

The 2025 hierarchy can be evaluated with one worksheet even though its media are unlike. Choose an application unit first: one generated token, loaded model, indexed object, protected transaction, synchronized file, or retained terabyte-year. For that unit, record latency and its tail, bytes read and written at every tier, compute or offload cycles, energy, occupied capacity, and recovery time. A device that wins one column may lose the complete unit.

The worksheet should include policy errors. Count prefetched bytes never used, cache entries returned after their deadline, objects promoted and soon evicted, compressed data expanded for no consumer, and offloaded work retried on the host. These are the costs hidden by peak throughput and average hit rate. They also show whether a learned or phase-aware controller remains useful after the workload changes.

Baseline selection deserves equal care. Compare a GPU filesystem with a tuned host-staging path, not an intentionally serialized copy. Compare a DPU index with the CPU and memory it actually replaces, including DPU power and memory. Compare glass and tape with the full migration and reader fleet, not only raw media price. Compare LPDDR or MRAM with the capacity, serviceability, and persistence behavior required by the platform.

Finally, classify every number as measured, modeled, or derived from structure. A measured chip point, a modeled fleet cost, and an interface peak can all be useful, but they carry different uncertainty. The 2025 papers make a persuasive case for specialization. The worksheet determines whether that specialization lowers total work for a specific system or merely moves it outside the reported boundary.

Run the worksheet at three timescales. A request-level view exposes late cache hits and synchronization. A job-level view exposes loading, preprocessing, checkpointing, and phase changes. A lifecycle view exposes media wear, model or software updates, migration, and repair. Optimizing one timescale can worsen another. A cache that reduces request latency may increase writes and shorten device life; an archive that lowers lifecycle cost can violate an urgent retrieval objective.

The evidence should also span three scales. Device measurements establish physical behavior. One-node or cluster experiments show integration. Fleet traces show population variance and operational cost. Not every research paper can provide all three, and absence at one scale is not a flaw by itself. The mistake is to silently extrapolate a measured result across the missing scales.

For procurement, attach an uncertainty range to every derived benefit. State which traffic, failures, and software work were measured and which were assumed. Then rerun the calculation with cache accuracy, compression ratio, device endurance, and offload utilization moved against the proposal. A specialized tier is robust when it still wins under plausible error, not only at the paper’s best point. This sensitivity test turns the annual literature map into a defensible engineering decision.

Complete 2025 company-paper index

ISSCC external memory, 6 records

  • 30.1, 4XX-layer 1 Tb TLC NAND at 28 Gb/mm² and 5.6 Gb/s/pin, Samsung Electronics.
  • 30.2, 1 Tb TLC NAND with 29% better read-energy efficiency and 4.8 Gb/s I/O, KIOXIA and Western Digital.
  • 30.3, 24 Gb 42.5 Gb/s GDDR7, Samsung Electronics.
  • 30.4, 16 Gb 12.7 Gb/s/pin LPDDR5 Ultra Pro, Samsung Electronics.
  • 30.5, 321-layer 2 Tb QLC NAND with 75 MB/s program throughput, SK hynix.
  • 30.6, 64 Gb DDR4-compatible STT-MRAM, KIOXIA and SK hynix.[1]

FAST storage systems, 15 records

  • Ananke, Microsoft Research and Wisconsin.
  • DJFS, Samsung Electronics, KAIST, and Wisconsin.
  • FlacIO, Huawei Technologies.
  • Cloudscape, NetApp and Wisconsin.
  • Mooncake, Moonshot AI and Tsinghua.
  • CPU/GPU billion-scale vector search, Huawei Technologies and collaborators.
  • IMPRESS, Huawei Cloud and Zhejiang University.
  • GeminiFS, Huawei Theory Lab and university collaborators.
  • 3L-Cache, Microsoft Research and collaborators.
  • HiDPU, Huawei Technologies and collaborators.
  • HaSiS, ScaleFlux and collaborators.
  • AtomicDisk, Ant Group and collaborators.
  • MedFS, OPPO and collaborators.
  • GogetaFS, Alibaba Group and collaborators.
  • PolyStore, Samsung Semiconductor and collaborators.[2]

ACM Transactions on Storage, 13 records

This editorial synthesis uses the official ISSCC program, open USENIX paper pages, and ACM publication records. It restates technical ideas and measurements in original language and reproduces no publisher figure or table. The explanatory plate was made for this article from a logo-free conceptual server image plus deterministic labels. ISSCC papers are © IEEE 2025. Rights for FAST and ACM TOS papers follow each linked record.