Memory-safe languages cannot immediately replace the installed base of C and C++. Arm’s Memory Tagging Extension (MTE) attaches a small tag to each allocation and pointer, then checks their match on memory access. The obstacle has been deployment cost. AmpereOne moves that cost into hardware already present for server reliability[1].

Tags without a reserved-memory tax

Conventional tag storage reserves part of DRAM capacity or adds a separate memory structure. AmpereOne co-locates tags with data by repurposing part of the protection-code budget, while preserving the required error-detection contract through microarchitectural changes. Load and store pipelines perform synchronous checks so a sequential buffer overflow is detected deterministically; randomly assigned tags give probabilistic protection against use-after-free errors.

Conceptual hardware view of AmpereOne MTE. Allocation tags are co-located with protected data rather than placed in a reserved DRAM region, and the core checks pointer and memory tags on access. The design reports no memory-capacity tax and single-digit performance impact. This is not a processor photograph or manufacturing drawing. Original figure created for this article.

Across tested datacenter workloads, the performance impact is in the mid single-digit range and memory capacity loss for tag storage is zero. The remaining overhead often comes from software allocation. The evaluation had to replace jemalloc, which lacked tagging support, with glibc malloc; small-object initialization and tagging then dominated several cases. That diagnosis is useful because it identifies a software optimization path rather than a fixed hardware penalty.

What we take from it

AmpereOne turns memory safety from an ISA checkbox into a full-stack deployment question. Efficient tag storage and synchronous checks establish a viable hardware floor, but allocators, kernels, and fleet policy determine the realized cost. The paper’s strongest conclusion is that the bottleneck moved: once hardware removes the capacity tax, ordinary memory-management software becomes the next architectural target.

Source and attribution

This digest uses original wording and a newly composed conceptual plate. It reproduces no paper text, figure, or table. The public arXiv version is CC licensed; the ISCA proceedings version is © IEEE 2026.