For two decades, the DRAM industry maintained a tidy caste system. Registered DIMMs served the datacenter, where capacity, serviceability and reliability commanded a premium; LPDDR served phones, where every picojoule mattered and the memory was soldered down for life. Between February and August 2026, three announcements dismantled most of the wall between those castes. At ISSCC, both Korean vendors showed working LPDDR6 silicon seven months after JEDEC ratified the standard[1][2][7]. At Hot Chips, NVIDIA detailed a flagship server CPU whose entire memory system is mobile-derived LPDDR5X in serviceable modules[3]. A day later, Samsung showed the same memory class computing inside its own banks, tripling LLM token throughput on an edge accelerator[4]. The common thread is the constraint that now organizes datacenter design: power.

Readers of our memory series will recognize where this fits. HBF is widening the hierarchy’s capacity floor and Raptor is raising its bandwidth ceiling; this article is about the third front, the CPU-side plane of the hierarchy, quietly switching to the lowest-power DRAM the industry makes. We summarize the three announcements in sequence and note what still separates LPDDR from the RDIMM incumbency it is crowding.

Seven months from standard to silicon

JEDEC ratified LPDDR6 in mid-2025, and by ISSCC in February 2026 both Samsung and SK hynix were presenting functional silicon, a turnaround of about seven months that mature DRAM generations rarely manage. The two implementations split the design space instructively. SK hynix pushed rate: a 16 Gb device on its 1c-nm process (its sixth 10 nm-class generation) running 14.4 Gb/s/pin at 1.025 V, with the company claiming 20% lower power and 50% higher bandwidth against its LPDDR5X[1][7]. Samsung tuned the other axis, presenting LPDDR6 at 12.8 Gb/s/pin with the design centered on power efficiency[2]. Note what the split implies: LPDDR6 is arriving not as one part but as a family with vendor-differentiated operating points, which is how server memory generations behave, not phone memory generations.

LPDDR6 arrives at server cadence. a, Seven months separate JEDEC ratification in mid-2025 from working silicon at ISSCC in February 2026. b, The first implementations split the design space: SK hynix runs a 16 Gb die on its 1c-nm process at 14.4 Gb/s/pin and 1.025 V, claiming 20% lower power and 50% more bandwidth than LPDDR5X, while Samsung centers its 12.8 Gb/s/pin part on power efficiency. Original figure created for this article.

The socket problem, solved by a module

What kept LPDDR out of servers was never speed; it was everything around speed. LPDDR came soldered, so a failed package meant a failed board. Capacity per attachment trailed what stacked RDIMMs offered, and the RAS machinery that datacenter operators trust (spare rows, error telemetry, field-replaceable units) grew up on the registered-DIMM side of the wall. NVIDIA’s Grace crossed the wall anyway by soldering LPDDR5X next to the CPU and accepting the serviceability cost. Vera, detailed at Hot Chips 2026, shows what the second iteration looks like: eight SOCAMM2 module slots per CPU, populated from 256 GB up to 1.5 TB, running LPDDR5X at up to 9600 MT/s for about 1.2 TB/s of aggregate bandwidth, twice Grace’s per-core bandwidth at 14 GB/s per core[3][5].

The power numbers explain the effort. Micron puts LPDDR5X at roughly one third the power of an equivalent RDIMM, and NVIDIA quotes the fully populated Vera memory subsystem at 30 to 40 W, on a CPU whose own TDP is configurable between 250 and 450 W[5]. In a rack where accelerators claim every available watt, tens of watts saved per CPU socket, multiplied across a fleet, is exactly the currency that buys more GPUs. SOCAMM2 restores the modularity half of the RDIMM bargain; the RAS track record, which registered DIMMs accumulated over decades, remains the part that only time in the field can supply.

Vera’s memory system is mobile silicon in server clothing. a, Eight SOCAMM2 module slots surround the CPU, populated from 256 GB to 1.5 TB of LPDDR5X at up to 9600 MT/s, restoring the field-serviceability that soldered Grace-style LPDDR gave up. b, The operating point: about 1.2 TB/s aggregate, 14 GB/s per core (2× Grace), a 30 to 40 W memory subsystem, and roughly one third of RDIMM power per Micron’s comparison. Original figure created for this article.

Memory that computes, in a standard package

The third announcement moves compute across the interface entirely. Inside any DRAM die, the banks collectively touch far more data per second than the external interface can carry; processing-in-memory (PIM) exploits that gap by planting arithmetic beside the banks. Samsung’s LPDDR5X-PIM, shown at Hot Chips 2026, distributes 16 PIM blocks across the die’s 16 banks, each with multiply-accumulate trees and an ALU handling both floating-point and integer formats, the first low-power PIM part with multi-precision support[4][6]. The internal figure is the story: 614 GB/s of PIM-side bandwidth against 76.8 GB/s through the conventional interface, an 8× gap that never leaves the package. On an edge accelerator running Llama 3.1 8B, token throughput rose from 27 to 81.3 tokens per second, a 3.01× gain, with the decode phase (i.e., the bandwidth-bound phase, as our Raptor coverage discussed) the natural beneficiary.

Two details signal that this is aimed beyond a demo. The part keeps the JEDEC-standard package, so it drops into existing LPDDR5X footprints without board changes. And the standardization machinery is already turning: Samsung and SK hynix are working through JEDEC on LPDDR6-PIM, with Micron also expected to bring PIM to the LPDDR6 generation, which would make computing memory a standard catalog item rather than a proprietary experiment.

Compute moves inside the package. a, Sixteen PIM blocks sit beside the die’s sixteen banks, each with MAC trees and a multi-precision ALU; the banks’ collective 614 GB/s dwarfs the 76.8 GB/s external interface, an 8× gap PIM exploits in place. b, The measured effect: Llama 3.1 8B token throughput rises from 27 to 81.3 tokens per second (3.01×) on an edge accelerator, in a JEDEC-standard package that drops into existing LPDDR5X footprints. Original figure created for this article.

What we take from it

Individually, each announcement reads as incremental: a faster generation, a new module, a lab demo. Together they describe a caste system ending. The same silicon class now iterates at server cadence, mounts in serviceable server modules, and is learning to compute, and all three moves are financed by the one metric HBM cannot win: energy per bit. We believe the near-term consequence is a bifurcated DRAM market in which HBM concentrates on the accelerator package (where Raptor-style stacking pressures it from above) while LPDDR absorbs the CPU plane and the capacity tiers that HBF has not claimed. The open questions are the unglamorous ones. RAS behavior at fleet scale has no LPDDR track record yet, per-socket capacity still trails big RDIMM configurations, and PIM’s programming model must convince software the way tiering software had to convince the Vistara generation. However, the direction has the feel of settled physics: when watts are the budget, the phone memory was always going to win the argument.

Source and attribution

This article is an editorial synthesis prepared for Silicon and Systems. It restates, in our own words, material presented publicly at ISSCC 2026 and Hot Chips 2026 and reported in the independent coverage cited above. No text, figures or slides from those sources are reproduced here, and the figures on this page were created for this summary. The referenced presentations are (c) their respective companies, 2026.