The 2025 public industry record is smaller than the 2024 set under the same filters, but its design direction is unusually consistent. Six papers place precision control inside the operation that creates the error. They do not wait for a large backend to repair reference ringing, PCM conductance error, sampling distortion, cable count, oscillator injection weakness, or retraining cost.
Scope and completeness
The inventory uses the same venue boundary as the 2024 review: ISSCC, VLSI Circuits, CICC, ESSERC Circuits, A-SSCC, and JSSC. We require a company affiliation in the published author record and an openly reachable full-text location. Official program tracks were checked for VLSI and ESSERC. Six works satisfied all conditions for 2025. The count describes this reproducible public subset, not the full volume of company-authored circuit research.
An asynchronous SAR pipeline fixes latency and reference behavior together
Analog Devices and KU Leuven split a low-noise SAR ADC into two stages and allow their decisions to progress asynchronously. The purpose is not merely throughput. The second stage adds precision without tying conversion latency to the external sample period. Reference snubbers at the clock-domain crossings damp settling and ringing for the sub-ADCs and floating-inverter residue amplifier.[1]
The 40 nm prototype reports 71.1 dB peak SNDR and 77 dB dynamic range at 200 MS/s while consuming 5.8 mW. Conversion latency remains 8 ns under the stated operating method, and the reported Schreier figure of merit is 179.4 dB. The result shows that reference distribution is part of converter architecture. A faster comparator cannot recover precision if the reference network is still moving when the next decision begins.
PCM programming approaches an analog weight
STMicroelectronics and Italian university collaborators treat a phase-change-memory cell as a continuously adjustable conductance rather than a small set of coarse states. Their programming algorithm iteratively approaches a target and validates the result on a 28 nm FD-SOI analog in-memory-compute prototype that performs 512 × 512 signed matrix-vector multiplications.[2]
The reported programmed-weight equivalent number of bits is 10.55. That number characterizes programming precision under the experiment, not the end-to-end accuracy of every neural network or the long-term stability of all conductance levels. Drift, temperature, array-scale distributions, and repeated-update cost remain system conditions. Still, a converter-quality metric above ten bits changes what can be assigned to the memory array and what must remain in digital compensation.
The sampling front end reaches Ka band without a mixer
The University of Twente and Teledyne built a four-way time-interleaved front end at 12.8 GS/s with 38 GHz tracking bandwidth. An inductor-assisted input network, push-pull buffers, and active bootstrapping extend the first track-and-hold. A single first-rank sampler avoids the skew and bandwidth-mismatch calibration that multiple parallel front samplers would require.[3]
Four measured samples maintained more than 39 dB SNDR through a 32 GHz input while the front end consumed 87 mW. The authors estimate about 25 fs of total aperture jitter, and the input return loss remains better than 12 dB through 35 GHz. This is enough to directly subsample the targeted 27-31 GHz satellite band. The architectural gain is the removed RF mixer, but the clock-jitter and input-network requirements move directly onto the ADC front end.
A 4096-element probe makes channel reduction a package function
The Philips collaboration expands its earlier 2048-element ultrasound chip into a probe containing two ASICs and a 23 × 23 mm², 4096-element CMUT array. Each ASIC serves 2048 elements. A 2 × 2 delay-and-sum micro-beamformer followed by 2× time-division multiplexing reduces receive channels by 8×, while an on-chip pseudorandom training sequence enables equalization that lowers TDM crosstalk by 10 dB.[4]
In the reported setup, the probe reaches 2000 volumes/s while covering 60° in both angular dimensions and 10 cm in depth. Receive and logic power are 0.85 and 0.10 mW per element, while nominal transmit power is 0.34 mW per element and depends on the waveform. The important progression from the 2024 conference chip is not only twice the element count. It is the demonstration that array, two ASICs, cable reduction, equalization, and transmit programmability can operate as one probe.
A PLL injects on both halves of the reference cycle
University College Dublin and MediaTek alternate two charge-sharing capacitors so that positive and negative reference half-cycles both reinforce the LC tank. This ping-pong path implicitly doubles the injection opportunity. A frequency-tracking loop and duty-cycle calibration keep the scheme operating across process, voltage, and temperature, while a low-power bang-bang detector supervises the adjustments.[5]
In 28 nm CMOS, the roughly 27 GHz PLL reports 42 fs rms jitter at 14 mW. The injection strength is three times that of the comparison charge-sharing structure, and the reference spur improves by about 15 dB. The reported jitter-normalized figure of merit is -276.6 dB. The mechanism matters more than the record value: both halves of a reference period become useful energy-transfer events, provided calibration keeps their timing and duty cycle aligned.
Continual learning replaces backpropagation with a searchable representation
The UC San Diego and TSMC Clo-HDnn accelerator targets learning after deployment. It combines a weight-clustered feature extractor with hyperdimensional computing, which stores learned classes as hypervectors rather than repeatedly updating a deep network by gradient descent. A Kronecker-product encoder compresses the representation cost, and progressive search stops after enough of the query hypervector has been compared.[6]
The chip reports 4.66 TFLOPS/W for feature extraction and 3.78 TOPS/W for classification. Progressive search reduces the evaluated work by as much as 61% under the reported tasks. Those efficiencies use different operation definitions and should not be collapsed into one number. The system result is that continual learning can be made predictable when the expensive feature extractor is reused and the update itself becomes a compact, gradient-free class representation.
The 2025 design pattern
All six works reduce the distance between an error and its correction. The ADC damps its reference crossing, PCM programming closes the loop on conductance, the Ka-band sampler removes an external frequency-conversion step, the probe reduces channels before its cable, the PLL reuses the otherwise idle reference half-cycle, and the learner updates hypervectors instead of a full model.
This suggests a practical evaluation rule. Ask not only how much precision or efficiency a chip reports, but also where its control loop terminates. A result is more likely to survive system integration when the variable being corrected remains local, observable, and bounded by the same hardware that created it.
Source and copyright notice
This article independently synthesizes the six cited papers. It restates their technical ideas and measured results in original language and does not reproduce publisher figures or tables. The conceptual hardware plate was generated for this article and labeled with code; it is not a photograph or layout of any reported device. The cited works are © IEEE 2025. Public manuscript access is not treated as a license to reuse the IEEE presentation.