Production Evidence Replaced the Architecture Promise: 42 Company-Affiliated Papers at ISCA 2026

ISCA 2026 contains unusually direct production evidence: deployed CXL memory, fleet Rowhammer defense, accelerator kernels, climate-aware cooling, and processors built around changing AI workloads. The 42 records in this review passed two checks: the title appears in the official conference program, and at least one publisher-supplied author affiliation directly names a commercial company or corporate research organization. That rule includes university-industry collaborations but excludes papers that merely acknowledge a vendor, authors whose current employer differs from the paper affiliation, and automatic institution matches that cannot be confirmed in the source metadata.[1]

The inventory is time-bounded through August 31, 2026. 5 records had an openly accessible full-text location in the discovery metadata; the remaining records are included only at the level supported by the official program and DOI metadata. We use open manuscripts for mechanism-level observations and do not reconstruct a closed paper from an abstract. Existing Silicon & Systems reviews remain linked through their DOI where available rather than being rewritten as duplicates.

What the publication count does and does not measure

A company affiliation is evidence that the work crossed an industrial research boundary. It is not evidence that the mechanism shipped, improved total cost, or survived a production workload. Some papers report fabricated silicon or deployed systems. Others present simulation, trace replay, emulation, compiler experiments, or analytical models. Those evidence classes answer different questions and cannot be ranked by one headline number.

The count also reflects publication practice. Meta (8), Huawei (6), NVIDIA (6), AMD (5), IBM (3), Intel (3), Microsoft (3), Samsung (3) appear most often in this verified set, but a company that publishes less may still deploy more. Large university collaborations can add many papers without transferring the mechanism into a product. For this reason, the complete index below preserves title, DOI, and corporate affiliation while the analysis focuses on recurring system decisions.

AI compute moved from peak arithmetic to resource contracts

The AI papers increasingly ask who controls memory, scheduling, precision, and failure recovery rather than how many operations a datapath can issue. Training and inference make different demands: training needs synchronized progress across large groups, while inference must protect latency under changing sequence length, batch size, and model state. A mechanism that improves one regime can waste capacity in the other.

The most transferable question is therefore the resource contract. A paper should identify which bytes remain resident, which work can be preempted, how much parallelism is required to reach the reported result, and what happens when the model or request distribution changes. Without those conditions, an accelerator speedup is difficult to translate into a server count or service-level objective.

Memory behavior became part of the architecture rather than an input

The memory papers span cache management, prefetching, address translation, disaggregation, storage paths, and data movement. This breadth reflects a common constraint: useful work is often limited by where state resides and when it moves, not by the peak rate of the execution units. Caches and prefetchers can reduce average latency while making interference or tail behavior harder to predict.

Production adoption needs a byte-and-time ledger. The platform should distinguish capacity saved from traffic added, local hits from remote service, average bandwidth from tail latency, and one-time migration from steady-state work. The same mechanism can look favorable in an isolated benchmark and become expensive when recovery, coherency, or multi-tenant isolation is included.

Compiler and runtime work became an architectural control plane

Compiler, runtime, and scheduling papers show that architecture is no longer fixed when the chip leaves fabrication. Kernel selection, graph partitioning, queue admission, placement, and code generation decide which hardware paths are exercised. This software control plane can recover performance from a general device, but it can also hide brittle assumptions about shapes, driver behavior, and workload repetition.

A credible evaluation should separate search cost from execution benefit, warm from cold behavior, and offline tuning from decisions made inside a service deadline. It should also test a hardware or model generation that was not used to design the policy. Otherwise the reported gain may be a successful fit to one benchmark rather than a reusable architectural mechanism.

Reliability and security need an explicit failure boundary

Security and reliability mechanisms often trade metadata, checks, sampling, or redundancy against performance. Their value depends on the failure model. A defense against one fault or attack pattern should not be read as general isolation, and a low average overhead does not reveal the worst recovery path or the state exposed during rollback.

The adoption checklist is concrete: define the protected state, the detector’s blind spots, the time to containment, the state that must be reconstructed, and the behavior when the detector itself fails. Fleet evidence is particularly valuable because it exposes background errors and operational constraints that simulation rarely includes. Even then, hardware generation and deployment policy limit transferability.

The operating decision behind this literature

Across the set, the architectural boundary moves only when another layer accepts new responsibility. More flexible hardware asks the compiler to supply better schedules. Disaggregated memory asks the runtime to place data and recover from remote faults. Shared accelerators ask the scheduler to expose interference and preemption. Security metadata asks the memory system to preserve tags through caches, DMA, and I/O.

This changes procurement and design review. Peak throughput should be accompanied by the minimum useful batch, residency requirement, worst queue delay, failure recovery cost, and software dependency. The paper that reports the largest speedup is not automatically the safest choice. The stronger candidate is the one whose assumptions match the operator’s workload and whose fallback remains measurable.

How to use the complete index

The index is grouped by the principal topic visible in each title. Several papers belong in more than one group; each appears once to keep the count auditable. A DOI link is a bibliographic record, not a statement that the full text is free to reuse. Readers should check the license on the specific manuscript before reproducing a figure or table.

The best follow-up candidates combine three properties: a mechanism that changes a system boundary, enough public evidence to preserve evaluation conditions, and an implication that matters beyond one product. Papers already covered by Silicon & Systems should be extended only when new evidence changes the judgment. The rest form a monitored backlog rather than a queue for shallow summaries.

Complete ISCA 2026 company-affiliated paper index

AI compute and model execution, 22 records

• Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs, Huawei.
• DIAMoND: Dynamic Inference for Adaptive Edge MOE with Heterogeneous In-NAND and Near-DRAM Compute Architecture, Xiaomi.
• Early Silicon of Raptor: The First 3D-DRAM Accelerator for Generative Inference, d-Matrix.
• ENEC: A Lossless AI Model Compression Method Enabling Fast Inference on Ascend NPUs, Huawei.
• HyperDrive: Hierarchical Exploitation of Memory Efficiency for GPU-Based FHE Acceleration, Ant Group.
• KernelEvolve: Scaling Agentic Kernel Coding for Heterogeneous AI Accelerators at Meta, Meta.
• LoKA: Low-Precision Kernel Applications for Recommendation Models at Scale, Meta.
• MNEMOS: A GPU-Based TFHE Acceleration Framework with Memory Access Optimization, Ant Group.
• MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems, Huawei.
• MTIA 300: Meta’s First Training Chip Featuring Built-in NICs and Collective Offloading Engines, Meta.
• MXFFP: Microscaling Flexible Floating Point Format for Large-Scale AI Model Acceleration, Meta.
• Patterns Behind Chaos: Forecasting Data Movement for Efficient Large-Scale Moe LLM Inference, Samsung, NVIDIA.
• PipeWeave: Synergizing Analytical and Learning Models for Unified GPU Performance Prediction, Alibaba.
• Power Sloshing in Compound Servers for Large-Scale AI Inference Workloads, Meta.
• PowerGrad: Hierarchical Power Management for Power-Limited ML Inference Clusters, IBM, AMD.
• QiMeng-Tensify: Scaling Up Tensor Computation Optimization via Architecture-Aware LLM-Guided MCTS, Cambricon.
• Scalable Synthesis of Distributed Llm Workloads Through Symbolic Tensor Graphs, NVIDIA.
• SHyLA: 3D-Stacked NVM-DRAM Hybrid LLM-Inference Architecture Exploiting Data and Memory Heterogeneity, Huawei.
• SLICE: A Selective Local Inference Framework with Codec Exploitation for Accelerating Video Super-Resolution, Samsung.
• STEP: Adaptive Spatio-Temporal Expert Prefetching for Low-Latency and Memory-Efficient MoE Inference, Alibaba.
• Tetris: Efficient Long-context LLM Serving with Chunkwise Dynamic Sequence Parallelism, ByteDance.
• Understanding Inference Scaling for LLMS: Bottlenecks, Trade-Offs, and Performance Principles, Micron.

Memory, storage, and data movement, 5 records

• AXLE: Coordinated Offloading with Asynchronous Back-Streaming in Computational Memory Systems, SK hynix.
• Dorado: Clustered Hardware Cache Coherence for 1,000+ Cores, Intel.
• Enhancing Instruction Prefetching via Cache and TLB Management, Huawei.
• Five-Minute Rule 40 Years Later: A First-Principles Revisit for Modern Memory Hierarchy, NVIDIA.
• Vistara: Making CXL Real-Full Path From ASIC Design and OS Support to Hyperscale Deployment, Meta.

Processors, accelerators, and execution, 8 records

• ATX: Accelerator Task Extensions, Intel.
• Bumper: Hinting Instruction Usefulness for Robust Unified Caches, Huawei.
• Distilling Magic States in the Bicycle Architecture, IBM.
• Enabling Continuous, in-Field Introspection: The Programmable IPU Architecture, NVIDIA.
• Lippen: a Lightweight in-Place Pointer Encryption Architecture for Pointer Integrity, Igalia.
• PipeIMC: A Pipelined In-SRAM Computing Architecture, Taihao HuiXin Microelectronics.
• PVAC: A Rowhammer Mitigation Architecture Exploiting Per-Victim-Row Counting, Samsung.
• SPEC CPU: The Next Generation, Ampere Computing, IEIT, Intel, AMD, Dell, IBM, VRULL, SPEC, Rivos, Arm, HPE, NVIDIA, SiFive.

Runtime, compiler, and scheduling, 1 records

• NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing, Lenovo Research.

Reliability, security, and verification, 2 records

• From Lab to Fleet: Building and Deploying a Practical Rowhammer Defense in Cloud SoCs, Microsoft, Meta.
• Loaded Dice: Solving the Non-Selection Problem for Scalable Probabilistic RowHammer Defense, NVIDIA.

Other architecture mechanisms, 4 records

• Lit Silicon: A Case Where Thermal Imbalance Couples Concurrent Execution in Multiple GPUs, AMD.
• PhaseWeave: Phase-Aware Execution on Heterogeneous Chiplet Architectures for Datacenters, Microsoft, Meta.
• Random-Access Hardware Sequence Compression, AMD.
• Taking Analytic Databases to the Bank, Microsoft, AMD, Micron.

Source and copyright notice

This time-bounded editorial synthesis uses the official ISCA 2026 program, Crossref DOI metadata, and OpenAlex discovery records verified against publisher-supplied affiliations. It restates no closed-paper mechanism beyond public metadata and reproduces no publisher prose, table, or figure. The conceptual hardware plate and deterministic labels were created for this article. Rights for each paper remain with its authors and publisher; follow the linked DOI for the authoritative record and license.