An automotive accelerator must run perception, planning, language, and cockpit models under a fixed vehicle power and cost envelope. A narrow DSA can be efficient today and obsolete after the next model change. Li Auto’s M100 aims for a middle point: tensor-granular dataflow whose schedule is explicit in software rather than discovered through a large GPU cache hierarchy[1].
Orchestrate movement, not cache misses
M100’s compiler and runtime schedule tensors through compute clusters, data-movement engines, on-chip memories, and external DDR. The architecture largely removes hardware-managed caching. Tensor size remains flexible, while coarser scheduling reduces instruction and synchronization overhead. The design relies on predictable model dataflow; irregular control still needs software handling.
Against NVIDIA Thor-U at the same power budget and identical 273 GB/s DDR bandwidth, M100 reports 1.2× to 6.3× speedups across UniAD components and 3.8× higher end-to-end frame rate. The tested chip activates eight of fourteen clusters for UniAD, leaving resources for concurrent work. Llama-2 7B decode is similar, 20 ms versus 21.34 ms, because external memory bandwidth dominates. Prefill numbers in the extracted table indicate Thor-U is faster, so the paper’s strongest evidence is workload-specific, not universal.
What we take from it
M100 shows where dataflow wins and where it cannot escape physics. Explicit orchestration keeps engines busy on structured perception graphs, but a bandwidth-bound decoder converges toward the same DDR ceiling. The architecture will succeed if its compiler adapts faster than automotive models change and if the saved cache complexity becomes deployable cost and power rather than new software fragility.
Source and attribution
This article is independently written and uses an original conceptual plate. No source figure, table, or text is reproduced. The authors provide a public arXiv manuscript; the proceedings version is © IEEE 2026.