The company record at ISCA 2025 is less a catalog of isolated chips than a record of architecture crossing into model training, inference fleets, memory systems, and procurement. The 43 records in this review passed two checks: the title appears in the official conference program, and at least one publisher-supplied author affiliation directly names a commercial company or corporate research organization. That rule includes university-industry collaborations but excludes papers that merely acknowledge a vendor, authors whose current employer differs from the paper affiliation, and automatic institution matches that cannot be confirmed in the source metadata.[1]
The inventory is time-bounded through August 31, 2026. 43 records had an openly accessible full-text location in the discovery metadata; the remaining records are included only at the level supported by the official program and DOI metadata. We use open manuscripts for mechanism-level observations and do not reconstruct a closed paper from an abstract. Existing Silicon & Systems reviews remain linked through their DOI where available rather than being rewritten as duplicates.
What the publication count does and does not measure
A company affiliation is evidence that the work crossed an industrial research boundary. It is not evidence that the mechanism shipped, improved total cost, or survived a production workload. Some papers report fabricated silicon or deployed systems. Others present simulation, trace replay, emulation, compiler experiments, or analytical models. Those evidence classes answer different questions and cannot be ranked by one headline number.
The count also reflects publication practice. Google (5), Meta (5), Samsung (5), Intel (4), AMD (3), Google DeepMind (3), MangoBoost (3), NVIDIA (3) appear most often in this verified set, but a company that publishes less may still deploy more. Large university collaborations can add many papers without transferring the mechanism into a product. For this reason, the complete index below preserves title, DOI, and corporate affiliation while the analysis focuses on recurring system decisions.
AI compute moved from peak arithmetic to resource contracts
The AI papers increasingly ask who controls memory, scheduling, precision, and failure recovery rather than how many operations a datapath can issue. Training and inference make different demands: training needs synchronized progress across large groups, while inference must protect latency under changing sequence length, batch size, and model state. A mechanism that improves one regime can waste capacity in the other.
The most transferable question is therefore the resource contract. A paper should identify which bytes remain resident, which work can be preempted, how much parallelism is required to reach the reported result, and what happens when the model or request distribution changes. Without those conditions, an accelerator speedup is difficult to translate into a server count or service-level objective.
Memory behavior became part of the architecture rather than an input
The memory papers span cache management, prefetching, address translation, disaggregation, storage paths, and data movement. This breadth reflects a common constraint: useful work is often limited by where state resides and when it moves, not by the peak rate of the execution units. Caches and prefetchers can reduce average latency while making interference or tail behavior harder to predict.
Production adoption needs a byte-and-time ledger. The platform should distinguish capacity saved from traffic added, local hits from remote service, average bandwidth from tail latency, and one-time migration from steady-state work. The same mechanism can look favorable in an isolated benchmark and become expensive when recovery, coherency, or multi-tenant isolation is included.
Compiler and runtime work became an architectural control plane
Compiler, runtime, and scheduling papers show that architecture is no longer fixed when the chip leaves fabrication. Kernel selection, graph partitioning, queue admission, placement, and code generation decide which hardware paths are exercised. This software control plane can recover performance from a general device, but it can also hide brittle assumptions about shapes, driver behavior, and workload repetition.
A credible evaluation should separate search cost from execution benefit, warm from cold behavior, and offline tuning from decisions made inside a service deadline. It should also test a hardware or model generation that was not used to design the policy. Otherwise the reported gain may be a successful fit to one benchmark rather than a reusable architectural mechanism.
Reliability and security need an explicit failure boundary
Security and reliability mechanisms often trade metadata, checks, sampling, or redundancy against performance. Their value depends on the failure model. A defense against one fault or attack pattern should not be read as general isolation, and a low average overhead does not reveal the worst recovery path or the state exposed during rollback.
The adoption checklist is concrete: define the protected state, the detector’s blind spots, the time to containment, the state that must be reconstructed, and the behavior when the detector itself fails. Fleet evidence is particularly valuable because it exposes background errors and operational constraints that simulation rarely includes. Even then, hardware generation and deployment policy limit transferability.
The operating decision behind this literature
Across the set, the architectural boundary moves only when another layer accepts new responsibility. More flexible hardware asks the compiler to supply better schedules. Disaggregated memory asks the runtime to place data and recover from remote faults. Shared accelerators ask the scheduler to expose interference and preemption. Security metadata asks the memory system to preserve tags through caches, DMA, and I/O.
This changes procurement and design review. Peak throughput should be accompanied by the minimum useful batch, residency requirement, worst queue delay, failure recovery cost, and software dependency. The paper that reports the largest speedup is not automatically the safest choice. The stronger candidate is the one whose assumptions match the operator’s workload and whose fallback remains measurable.
How to use the complete index
The index is grouped by the principal topic visible in each title. Several papers belong in more than one group; each appears once to keep the count auditable. A DOI link is a bibliographic record, not a statement that the full text is free to reuse. Readers should check the license on the specific manuscript before reproducing a figure or table.
The best follow-up candidates combine three properties: a mechanism that changes a system boundary, enough public evidence to preserve evaluation conditions, and an implication that matters beyond one product. Papers already covered by Silicon & Systems should be extended only when new evidence changes the judgment. The rest form a monitored backlog rather than a queue for shallow summaries.
Complete ISCA 2025 company-affiliated paper index
AI compute and model execution, 14 records
- Cambricon-SR: An Accelerator for Neural Scene Representation with Sparse Encoding Table, Cambricon.
- Debunking the CUDA Myth Towards GPU-based AI Systems, SqueezeBits, NAVER Cloud.
- Forest: Access-aware GPU UVM Management, NVIDIA.
- FRED: A Wafer-scale Fabric for 3D Parallel DNN Training, Intel.
- GPUs All Grown-Up: Fully Device-Driven SpMV Using GPU Work Graphs, AMD.
- LIA: A Single-GPU LLM Inference Acceleration with Cooperative AMX-Enabled CPU-GPU Computation and CXL Offloading, Google DeepMind.
- LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference, Microsoft.
- Meta’s Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences, Meta.
- Neo: Towards Efficient Fully Homomorphic Encryption Acceleration using Tensor Core, Ant Group.
- NetCrafter: Tailoring Network Traffic for Non-Uniform Bandwidth Multi-GPU Systems, MangoBoost.
- Scaling Llama 3 Training with Efficient Parallelism Strategies, Meta.
- Topology-Aware Virtualization over Inter-Core Connected Neural Processing Units, SenseTime.
- TRACI: Network Acceleration of Input-Dynamic Communication for Large-Scale Deep Learning Recommendation Model, Samsung.
- TrioSim: A Lightweight Simulator for Large-Scale DNN Workloads on Multi-GPU Systems, Lightmatter.
Memory, storage, and data movement, 5 records
- ANVIL: An In-Storage Accelerator for Name–Value Data Stores, Micron.
- CORD: Low-Latency, Bandwidth-Efficient and Scalable Release Consistency via Directory Ordering, NVIDIA.
- Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-Aware Cache Compression, AMD.
- Folded Banks: 3D-Stacked HBM Design for Fine-Grained Random-Access Bandwidth, AMD, Microsoft.
- Heliostat: Harnessing Ray Tracing Accelerators for Page Table Walks, Samsung.
Processors, accelerators, and execution, 9 records
- A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices, Meta.
- AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM, Houmo AI.
- Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion, Google, Google DeepMind.
- Dynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements, and Guidelines, Meta, Intel.
- FAST:An FHE Accelerator for Scalable-parallelism with Tunable-bit, Ant Group.
- FlexNeRFer: A Multi-Dataflow, Adaptive Sparsity-Aware Accelerator for On-Device NeRF Rendering, Samsung, DEEPX, Fitogether.
- Leveraging control-flow similarity to reduce branch predictor cold effects in microservices, Huawei.
- Qtenon: Towards Low-Latency Architecture Integration for Accelerating Hybrid Quantum-Classical Computing, ByteDance.
- Reconfigurable Stream Network Architecture, Google, MangoBoost.
Reliability, security, and verification, 2 records
- CaliQEC: In-situ Qubit Calibration for Surface Code Quantum Error Correction, AWS Quantum Technologies.
- MoPAC: Efficiently Mitigating Rowhammer with Probabilistic Activation Counting, Google.
Datacenter, network, and system policy, 1 records
Other architecture mechanisms, 12 records
- Avant-Garde: Empowering GPUs with Scaled Numeric Formats, MangoBoost.
- Constant-Rate Entanglement Distillation for Fast Quantum Interconnects, QuEra.
- Hermes: Algorithm-System Co-design for Efficient Retrieval-Augmented Generation At-Scale, NVIDIA.
- MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization, Intel.
- Neoscope: How Resilient Is My SoC to Workload Churn?, Bosch.
- Profile-Guided Temporal Prefetching, Intel.
- RAGO: Systematic Performance Optimization for Retrieval-Augmented Generation Serving, Google, Google DeepMind.
- Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays, QuEra.
- Rethinking Prefetching for Intermittent Computing, Samsung.
- RTSpMSpM: Harnessing Ray Tracing for Efficient Sparse Matrix Computations, Google.
- SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization, Samsung.
- SwitchQNet: Optimizing Distributed Quantum Computing for Quantum Data Centers with Switch Networks, Cisco.
Source and copyright notice
This time-bounded editorial synthesis uses the official ISCA 2025 program, Crossref DOI metadata, and OpenAlex discovery records verified against publisher-supplied affiliations. It restates no closed-paper mechanism beyond public metadata and reproduces no publisher prose, table, or figure. The conceptual hardware plate and deterministic labels were created for this article. Rights for each paper remain with its authors and publisher; follow the linked DOI for the authoritative record and license.