The 2026 record is larger because the hierarchy is changing at several boundaries at once. Ten company papers in the principal ISSCC memory session covered HBM4, LPDDR6, GDDR7, vertical DRAM, NAND, SRAM, MRAM, and TCAM. Twenty-three company-affiliated FAST papers addressed local cloud storage, tape, AI I/O, page cache, KV cache, file synchronization, zoned UFS, SSD failure, and Linux integrity. Nineteen ACM Transactions on Storage records extended the picture into HBM error prediction, mobile flash, cloud indexing, memory pooling, compression, deduplication, and PIM.

This article freezes the inventory at August 30, 2026. “All” means all records meeting the stated venue, date, public-metadata, and company-affiliation filters by that cutoff. Later journal assignments and conference proceedings can add to the year. Processor-local SRAM and compute-in-memory outside the principal memory session remain in the annual circuit index. Existing Silicon & Systems articles on AITURBO, Mooncake, LPDDR servers, HBM alternatives, and related CXL systems are linked instead of being duplicated.

A conceptual memory and storage server shows packages, memory slots, controllers, and NVMe devices while a deterministic overlay counts 52 company-affiliated ISSCC, FAST, and ACM TOS records through August 30, 2026. It is not a product photograph. Original figure created for this article.

HBM4 moved calibration inside every channel

Samsung’s 36 GB HBM4 reported 3.3 TB/s and used per-channel TSV read-data-strobe auto-calibration plus programmable memory built-in self-test. HBM obtains bandwidth from a wide interface and vertical integration, but more channels and more TSV paths create more local variation. Per-channel calibration treats that variation as an operating condition, not a one-time manufacturing exception.[1]

The 3.3 TB/s value is a stack-interface result. It is not guaranteed application bandwidth. A processor must generate enough independent requests, the package must deliver power and remove heat, and the memory controller must keep useful traffic on the interface. Error correction, refresh, bank conflicts, and software locality reduce the gap between theoretical and delivered bandwidth in workload-dependent ways.

The adjacent papers clarify HBM’s system role. Samsung’s vertical-cell-transistor 4F² DRAM placed cells over peripheral logic using wafer-to-wafer hybrid copper bonding. This attacks density and routing from the cell geometry upward. HBM4 attacks aggregate bandwidth from the package downward. Both make bonding, test, thermal behavior, and repair part of the memory architecture rather than post-design packaging details.

LPDDR6 spent width and modes to protect energy

SK hynix reported a 16 Gb LPDDR6 at 14.4 Gb/s per pin. Its efficiency mode, LDO-based write-clock tree, dynamic write termination, fast chip-select control, and system metadata mode target the energy and coordination costs around the data transfer. Samsung reported a 16 Gb LPDDR6 at 12.8 Gb/s with 12 data wires per subchannel, per-row activation counting, and a metadata scheme for reliability.[1]

The two papers should not be reduced to 14.4 versus 12.8. Channel width, operating mode, termination, reliability tracking, and controller behavior determine platform energy and usable capacity. Our LPDDR server analysis examines why low-power memory is moving into serviceable server modules. The 2026 silicon papers show the device-side mechanisms that make that system argument possible.

SK hynix’s 24 Gb GDDR7 reached 48 Gb/s and added symmetric two-channel operation and reliability features for mid-range inference. GDDR sits between the wide, expensive HBM stack and lower-power LPDDR. Its value depends on whether board-level bandwidth, capacity, and power match the inference model and batch regime. A product comparison must therefore use delivered tokens per joule or task latency, not memory pin rate alone.

NAND and persistent memories divided the capacity market

Sandisk and KIOXIA reported a 2 Tb QLC, six-plane 3D NAND at 37.6 Gb/mm² with more than 85 MB/s write throughput. The six-plane organization increases parallel opportunity, while QLC and high density increase the controller’s responsibility for coding, placement, and maintenance. The paper establishes a silicon point; workload endurance and sustained performance remain system questions.[1]

Samsung’s 8 nm embedded MRAM reached 125 MHz and 19.94 Mb/mm² at 0.60 V. TSMC’s 16 nm embedded STT-MRAM provided 168 Mb, dual-port access, and 51.2 Gb/s read throughput. MediaTek’s 2 nm SRAM operated from a 350 mV single rail, and Renesas reported a configurable 3 nm TCAM. These are not substitutes for HBM or NAND. They place durable state, lookup, or low-voltage working memory next to a particular compute function. The hierarchy gains more specialized tiers even as software tries to present one address or object space.

AI I/O became schedulable work

Huawei’s grouped-I/O paper, reviewed separately as AITURBO, exposed related reads and writes as one operation so storage could optimize the job rather than independent requests. Huawei also moved LLM model loading into a programmable page cache. Samsung’s Seneca targeted data preprocessing. CacheSlide and Bidaw used model-serving context to manage KV-cache reuse and computation-storage interaction.[2]

These systems share one decision: storage needs information above the block request. A job identifier, model position, tensor lifetime, or reuse probability can change admission and scheduling. The risk is coupling. A policy optimized for one framework can become a liability after the model, batch size, or serving engine changes. Therefore, the interface should expose intent while preserving a safe generic path.

FAST also showed that loading, preprocessing, and checkpoint-adjacent traffic are different phases. A system that maximizes sequential bandwidth may still delay a latency-sensitive model start. A cache with a high average hit rate may return useful state too late. Grouped I/O is valuable when the group matches the application’s dependency graph, not simply because requests arrive together.

Cloud storage exposed its physical media again

Alibaba and Solidigm described the evolution of local storage in cloud systems. Huawei reported a deployed archive cloud using tape. Apple described ACOS, a geo-distributed object store at exabyte scale. Alibaba’s PolarStore compressed cloud-native database data, while ByteDance moved garbage collection into an explicit discard-based design for distributed log-structured storage.[2]

These papers reverse the idea that the cloud hides hardware. Local SSD selection affects failure and replacement. Tape changes retrieval and migration policy. Geo-distributed object storage pays in consistency and repair traffic. Compression changes CPU use, network movement, and failure recovery. At scale, the service is an agreement among media physics, software policy, and operations.

RASK and ThinkAhead attacked index and startup latency in cloud block storage. Alibaba Cloud’s SkySync and ParaSync used delta generation and fine-grained parallelism for file synchronization. KylinSoft’s CoFS and RosenBridge shortened container startup and virtualization I/O paths. A common pattern appears: when media latency falls, namespaces, images, synchronization, and virtualization become the remaining movement tax.

Zoned storage crossed from SSDs into phones

SK hynix and Google co-designed optimizations for zoned UFS, bringing host-managed placement to mobile storage. Samsung and Western Digital collaborators characterized flexible data placement SSDs with WARP. Google and Wisconsin used mirror-optimized tiering. These systems give software more control over where data lands, hoping to reduce internal garbage collection and improve isolation.[2]

More control also creates more responsibility. Software must group data by lifetime, handle zone capacity, recover metadata, and remain correct when hints are imperfect. The journal records reinforce this boundary. Samsung’s advanced I/O stack targeted zone-based mobile flash; Longsys participated in ConZone+ for practical zoned emulation; SmartX participated in ZNSlice for multi-tenant partitioning. The useful abstraction is not “zones are faster.” It is “placement intent can reduce device work when the system can maintain it.”

Reliability moved from counters to joint evidence

Samsung and Tencent’s FailureMiner combined decision evidence for SSD failure prediction. Samsung’s Linux data-integrity paper strengthened end-to-end protection in the I/O stack. The TOS article “Looking Back to Move Forward” used HBM error history to predict future failures with Huawei participation. Dell’s Argus targeted resemblance detection for post-deduplication delta compression, where a false or missed match affects efficiency and recovery behavior.[2][3]

Prediction is not protection by itself. A useful predictor must state lead time, false-positive cost, affected population, and the action taken after an alert. Integrity must cover data and metadata across CPU memory, interconnect, controller, media, replication, and recovery. The more dynamically the hierarchy moves data, the more important a stable end-to-end identity becomes.

The control plane must be observable and reversible

The 52 papers lead to three operational requirements.

First, every placement decision needs attribution. Operators should know whether a page, object, KV prefix, model shard, or file entered a tier because of policy, pressure, a hint, or failure recovery. Without attribution, a hierarchy cannot be debugged.

Second, every specialized path needs a fallback. GPU filesystems, DPUs, programmable page caches, zoned placement, and PIM can reduce movement, but the system must preserve correctness when the accelerator or hint is unavailable.

Third, movement needs an integrity envelope. Checksums, ordering, version identity, and recovery state must survive tier transitions. A faster boundary that weakens diagnosis or repair is not a system improvement.

More records do not mean one technology won

The rise from 34 indexed records in 2025 to 52 through August 2026 reflects broader publication at several layers, not a single breakthrough. HBM4, LPDDR6, vertical DRAM, and dense NAND advanced device boundaries. FAST 26 had more company-affiliated regular papers on cloud and AI storage. ACM TOS published several conference extensions and online-first records. These are publication counts, not market-share or quality scores.

The distinction is important because a large literature can indicate fragmentation. More specialized tiers create more interfaces, policies, and failure states. HBM4 and LPDDR6 solve different power and bandwidth problems. Zoned UFS and FDP SSDs expose different placement controls. Tape and geo-distributed object storage optimize different lifetimes. A buyer should resist interpreting publication volume as convergence on one architecture.

The useful signal is the recurring mechanism across venues. Device papers added local calibration and metadata. System papers exposed job, object, model, or lifetime intent. Journal papers studied longer-term reliability and index behavior. All three move decisions toward the layer with the best information while demanding a stronger end-to-end contract.

RAS moved into normal operation

Reliability, availability, and serviceability were once described as overhead around a fast datapath. The 2026 memory papers make them part of the normal datapath. Samsung’s HBM4 calibrates per-channel TSV timing and includes programmable MBIST. Its LPDDR6 counts row activations and carries metadata. SK hynix’s GDDR7 adds reliability features for inference. These mechanisms consume area, power, pins, cycles, or controller state because the operating margin is too valuable to leave unmanaged.

Operational RAS requires telemetry that preserves context. A corrected error should identify channel, bank, row, temperature, operating rate, and age. A calibration update should be correlated with workload and voltage conditions. Without context, a fleet sees counters but cannot separate a weak component from an aggressive operating point or a software access pattern.

Serviceability also changes with packaging. A stacked HBM component is not replaced like a DIMM. LPDDR attached to a board differs from serviceable low-power modules. Embedded MRAM and vertical DRAM are part of a die or bonded assembly. The system needs sparing, retirement, checkpointing, and replacement policies matched to the physical unit that can actually be serviced.

AI data paths need a phase model

The 2026 AI-storage papers can be organized by phase. Before execution, model loading and image preparation determine startup. During execution, KV-cache lookup and vector retrieval determine whether compute waits or recomputes. Between jobs, checkpoints, synchronization, compression, and garbage collection compete for bandwidth. During recovery, replicas and durable metadata determine restart time.

A benchmark that mixes these phases into average throughput can reward the wrong design. A page cache tuned for model loading may evict KV state needed moments later. Aggressive prefetch can accelerate startup while delaying a checkpoint. Compression can reduce network bytes while consuming CPU needed for request scheduling. The control plane needs phase identity or an equivalent signal to arbitrate these conflicts.

Phase-aware scheduling should still be bounded. Foreground inference cannot starve durability indefinitely. Checkpoint traffic cannot consume every device queue during a latency spike. Background garbage collection cannot wait until free space is exhausted. A practical system defines service objectives and reserves for each phase, then reports violations rather than only aggregate utilization.

Placement hints are contracts, not commands

Zoned UFS, FDP SSDs, ZNSlice, and related journal work give software more influence over physical placement. The device may use a hint to group similar lifetimes, select a placement handle, or keep tenants apart. Treating the hint as an absolute command is dangerous because device health, free space, and internal parallelism can change.

A robust interface makes the contract explicit. Software states intent such as expected lifetime, isolation group, sequentiality, or recovery priority. The device reports whether it accepted the hint and exposes enough telemetry to measure the result. Either side can fall back without corrupting data. This is stronger than an undocumented heuristic and safer than forcing software to manage physical flash geometry directly.

The same contract applies to cloud tiering. An application can state that an object is reconstructible, latency-critical, or retained for compliance. The service can choose local SSD, remote object storage, disk, or tape according to current conditions. Correctness depends on preserving the stated durability and retrieval objective while placement changes.

Prediction needs an action policy

FailureMiner and the HBM error-history study illustrate the difference between identifying risk and improving availability. A model can rank devices or components by predicted risk, but the fleet still needs an action policy. Retiring too early wastes capacity and creates migration traffic. Retiring too late increases uncorrectable failures. Throttling or recalibrating may preserve a component without moving data.

An action policy should include prediction horizon, confidence, migration duration, spare capacity, correlated-risk groups, and service impact. It should also record counterfactuals: whether an alerted device would actually have failed and whether an unalerted failure was missed. Without this feedback, the model cannot be calibrated across hardware generations.

HBM raises a particular challenge because errors can arise from DRAM cells, TSVs, package connections, power delivery, thermal gradients, or controller behavior. A single aggregate error count may combine failure modes that require different actions. The public study is valuable because it treats history as evidence; deployment must preserve enough structure in that history to choose the right intervention.

Compression and deduplication became shared infrastructure

PolarStore, the ByteDance garbage-collection work, Argus, HyTorC, the learning-based compressed ZNS SSD, and the paper arguing that deduplication can speed filesystems all manipulate the number and placement of physical bytes. At cloud scale, data reduction affects network, cache, replication, repair, and media lifetime at the same time.

The control loop needs a full byte ledger. It should record logical input bytes, physical data bytes, metadata, temporary rewrite space, network bytes, and bytes read during recovery. CPU, DPU, or controller cycles used by reduction belong in the same ledger. A smaller on-device footprint can still cost more if it increases compute or repair traffic beyond the saved media.

Shared reduction also changes failure coupling. Many logical objects can depend on one chunk, dictionary, or compressed extent. Corruption or deletion can therefore have a larger blast radius. Verification, reference accounting, and repair priority must scale with that sharing. Efficiency and reliability cannot be evaluated as separate features.

An operator checklist for a moving hierarchy

Before adopting one of these mechanisms, an operator can ask six concrete questions. What is the authoritative copy? Which component made the placement decision? What telemetry explains that decision? How does the system fall back? Which integrity checks cross the transition? How long does recovery take under the same load that motivated the optimization?

The answers should be testable. A diagram is insufficient if logs cannot identify the path of a real request. A fallback is insufficient if it has never been exercised at production scale. A checksum is insufficient if metadata or version identity sits outside its coverage. Recovery time is insufficient if migration traffic causes a second outage elsewhere.

This checklist separates promising mechanisms from operable products. The 2026 literature provides strong measured points and several deployment accounts, particularly in cloud storage. It remains uneven on long-duration mixed-vendor operation, policy interactions across multiple tiers, and lifecycle serviceability of advanced packages. Those gaps define the next evaluation program rather than invalidating the published work.

How the cutoff and duplicates were checked

ISSCC records came from the official 2026 advance program and were limited to the principal memory session. FAST records came from regular paper entries on the official technical-session page. ACM TOS records used first publication through August 30 and verified commercial affiliations in the author metadata. Keynotes, panels, introductions, and university-only works were excluded.

Several records also have dedicated or earlier coverage. The FAST grouped-I/O paper maps to AITURBO. Mooncake’s journal extension maps to the existing Mooncake review. LPDDR6 and HBM4 appear in broader platform analyses. These records remain in the annual publication index because they are part of the literature, but the site does not create a second article that repeats the same mechanism.

The 2026 count can change after the cutoff. An online-first TOS article may enter an issue without becoming a new record, while a genuinely new DOI or late conference proceeding can add one. The editorial ledger stores the date and venue rule so a later update can distinguish new evidence from a rebucketed publication.

Complete 2026 company-paper index through August 30

ISSCC memory, 10 records

  • 15.1, 2 Tb QLC six-plane 3D NAND at 37.6 Gb/mm² and above 85 MB/s write, Sandisk and KIOXIA.
  • 15.2, 350 mV single-rail 2 nm SRAM, MediaTek.
  • 15.3, 8 nm embedded MRAM at 125 MHz and 19.94 Mb/mm², Samsung.
  • 15.4, 168 Mb dual-port embedded STT-MRAM at 51.2 Gb/s, TSMC.
  • 15.5, 3 nm configurable TCAM, Renesas Electronics.
  • 15.6, 36 GB 3.3 TB/s HBM4, Samsung Electronics.
  • 15.7, 16 Gb 14.4 Gb/s/pin LPDDR6, SK hynix.
  • 15.8, 16 Gb 12.8 Gb/s LPDDR6, Samsung Electronics.
  • 15.9, 24 Gb 48 Gb/s GDDR7, SK hynix.
  • 15.10, vertical-cell-transistor 4F² DRAM with cell-on-peripheral bonding, Samsung Electronics.[1]

FAST storage systems, 23 records

ACM Transactions on Storage, 19 records

This time-bounded editorial synthesis uses official ISSCC and USENIX pages plus ACM publication metadata available through August 30, 2026. It paraphrases ideas and measurements in original language and reproduces no publisher figure or table. The explanatory hardware plate was created for this article with deterministic labels and is not a disclosed product design. ISSCC papers are © IEEE 2026. FAST and ACM TOS rights follow each linked record.