The unit of competition in AI infrastructure has quietly moved from the chip to the rack. Whoever defines how a few hundred accelerators inside that rack read each other’s memory collects a growing share of the bill: by one estimate in the UALink Consortium’s own commissioned analysis, $15 to 25 M of a $100 M deployment now goes to interconnects[2]. NVIDIA holds the incumbent position with NVLink, and since October 2024 an unusually broad coalition (a board drawing AMD, Intel and Synopsys from silicon, Alibaba, AWS, Google, Meta and Microsoft from the cloud, plus Apple, Astera Labs, Cisco and HPE, with over 115 members in total) has been building the open challenger, UALink. The consortium published its 200G 1.0 specification in April 2025 with a white paper by AMD’s Nathan Kalyanasundharam[1], and followed in January 2026 with a longer third-party analysis that, unusually for consortium literature, names its rivals and argues against them line by line[2]. This article reads both documents closely, and places them against the Ethernet counteroffensive and the one scale-up fabric already running at supernode scale in production, Huawei’s Unified Bus.
What UALink 1.0 actually defines
Strip the advocacy and the specification makes concrete, checkable commitments. UALink is a memory-semantic fabric: accelerators issue reads, writes and atomics of 64 to 256 bytes against a 57-bit fabric address space (128 PB), under the same ordering model that applies to an accelerator’s local memory, so a pod of up to 1,024 endpoints programs like one very large device rather than a network[1][2]. Each endpoint carries a 10-bit routing identifier; switches route by destination, and a pod can be carved into isolated virtual pods by partitioning switch ports. The stack is four thin layers. A protocol interface (UPLI) hands 64-byte flits to a transaction layer that compresses addresses with a streaming cache; the data link layer packs ten of those into a 640-byte flit protected by CRC-32 with link-level replay; the physical layer aligns each such flit to one RS(544,514) forward-error-correction codeword and ships it over standard IEEE 802.3 signaling at 212.5 GT/s per lane (200 GT/s of data), with a latency-reducing reduction of FEC interleaving as one of the few deviations from stock Ethernet[1].
The design targets follow from those choices: four lanes form an 800 Gbps-per-direction station, request-to-response round trips stay under 1 µs over copper runs below 4 meters spanning one to four racks, and protocol efficiency reaches 93% of physical bandwidth, illustrated in the white paper by 256-byte writes with completions riding 20 useful flits out of 21[1][2]. Two less-advertised inclusions deserve notice. UALinkSec specifies end-to-end encryption and authentication of all protocol channels, designed to hold even against a physically present adversary and to slot into confidential-computing TEEs, which reads like a hyperscaler procurement checkbox written into silicon. Manageability, likewise, is delegated to existing datacenter machinery (a pod controller driving switches through SAI, nodes through Redfish) rather than a new proprietary stack.
Equally instructive is what the documents decline to define. Inter-pod communication is explicitly out of scope. Ring and torus topologies are permitted but deadlock avoidance on them is the implementer’s problem. The software ecosystem above the fabric (collective libraries, the NCCL equivalent) belongs to members, not to the specification. In addition, every performance number in circulation is a target validated by modeling and protocol simulation: the January 2026 analysis states plainly that empirical multi-vendor verification is planned for 2026, with evaluation switch silicon expected late in the year[2]. UALink today is a completed paper standard awaiting its first hardware referendum.
The incumbent and the two counterattacks
NVLink remains the benchmark the documents measure against: 1.8 TB/s per GPU in its fifth generation, NVSwitch domains of 72 GPUs shipping in volume with configurations to 576 on the roadmap, and a decade of NCCL and CUDA maturity that no specification can conjure[2]. NVIDIA’s most telling move came in May 2025 with NVLink Fusion, which licenses selected partners to implement NVLink-compatible interfaces. The consortium’s analysis is quick to note that Fusion opens the interface without opening the standard (NVIDIA keeps certification, evolution and per-partner terms), but the concession itself acknowledges that a closed fabric had become a procurement liability at nine-figure deployment sizes.
The second counterattack came from Ethernet, and it arrived in a single crowded year: the Ultra Ethernet Consortium’s 1.0 specification in June 2025 with credit-based flow control and link-layer retry, Broadcom’s Scale-Up Ethernet framework contributed to OCP in September, and ESUN, an OCP initiative to standardize Ethernet scale-up networking, in October[4][5][6]. The UALink analysis meets this camp with two architectural distinctions rather than a dismissal. First, addressing: the Ethernet side leaves the fabric as pure transport, with address translation belonging to each accelerator vendor (SUE says so outright), while UALink defines one fabric-level address space every compliant device shares, which matters precisely in the multi-vendor deployments both camps claim to serve[2][4]. Second, flow control: Ethernet’s CBFC runs one credit loop per link, while UALink stacks independent credit domains at every boundary (six in a single-hop path), buying finer backpressure at the cost of complexity the specification must contain. Note the sociology underneath: Meta and Microsoft sit on UALink’s board while anchoring ESUN, and Broadcom sells the merchant silicon either way. The hyperscalers are not choosing a winner; they are financing an auction.
Standing apart from both is the one system already operating at the scale everyone else is specifying toward. Huawei’s CloudMatrix 384 connects 384 Ascend NPUs and 192 CPUs into a single supernode over its Unified Bus, and the UB-Mesh work extends the ambition to datacenter scale with a converged scale-up/scale-out protocol that Huawei has said it will open[8]. Whatever one makes of its ecosystem, it is the only entry on this map with production supernodes rather than projections.
The demand side has already published its order
What makes this standards race legible is that the customers have written down what they want, in venues we have covered. DeepSeek’s ISCA paper prices the scale-up domain in tokens per second (a 67 token/s decode ceiling on 400G NICs against roughly 1,200 inside an NVL72-class domain) and asks for exactly what a UALink-shaped fabric offers: memory semantics with hardware ordering, acquire/release in place of fences, and one converged domain instead of an NVLink-InfiniBand seam[7]. However, the same wishlist also demands in-network broadcast and reduction for MoE dispatch and combine, and UALink 1.0 specifies no in-network computation at all; collectives remain a software problem above the fabric. That gap is worth watching, since NVIDIA’s switches already do reduction in hardware. From the opposite flank, the InfiniteHBD argument shows a fabric needs no switch at all if ring all-reduce is the only traffic that matters, at 31% of NVL-72’s interconnect cost[9], a reminder that UALink’s any-to-any generality is a bet that EP-style traffic, not just TP rings, will define the rack. And beneath both sits the CXL layer this site follows closely: the January analysis itself positions UALink between the node-local tier (PCIe, CXL) and the scale-out network, and its 128 PB address space is sized with disaggregated and CXL-expanded memory in mind[2]. The one-chip datacenter argument and UALink are, in that reading, adjacent floors of the same building rather than rivals.
What we take from it
Specifications are promises, and 2026 is when UALink’s come due. We would watch three things. First, the silicon: evaluation switches are slated for late 2026, and the distance between a 93% modeled efficiency and a measured one, across vendors who have never interoperated, is where open standards historically stumble or prove themselves. Second, the software: NVLink’s real moat in 2026 is not the SerDes but NCCL, and the consortium’s bet that parallel multi-vendor software development beats a decade of single-vendor tuning remains unevidenced. Third, the board members’ own purchase orders: the same companies fund UALink, UEC and ESUN, and the first hyperscaler that deploys a non-NVLink scale-up domain at production scale will reveal which specification was the plan and which was the hedge. We believe the structural argument favors the open side eventually (a rack fabric priced like Ethernet and governed like PCIe is hard to beat on TCO once it exists), but “once it exists” is the entire question this year. The paper war is over and UALink won it; the silicon war has not started.
Sources and disclosure
This article is an original analysis by Silicon and Systems, based on the public documents cited below, principally the UALink Consortium’s April 2025 specification white paper and its January 2026 commissioned technical analysis. No text or figures from those documents are reproduced; the figures on this page were created for this article. Disclosure: the editor of this site is CEO of Panmnesia, a company building CXL fabric silicon discussed in adjacent coverage; this article touches the CXL layer only peripherally, but read our framing with that interest in mind.