AMD’s first exascale node did not use the integrated processor that its research program originally imagined. Frontier instead connected separate EPYC CPUs and Instinct GPUs because packaging, yield, and product schedules made a single large APU impractical. The ISCA 2024 paper is valuable because it explains how that abandoned idea returned as MI300A, and which physical constraints had to change before integration became rational[1].
One address space changes the node
MI300A combines six CDNA 3 accelerator complex dies, three Zen 4 CPU dies with 24 cores, four base I/O dies, and eight HBM3 stacks. The 128 GB memory pool supplies about 5.3 TB/s and is coherent across CPU and GPU agents. A CPU can initialize a dataset in HBM and a GPU can consume it without copying the allocation through host DRAM. That is the architectural result. The package is not merely a smaller version of a discrete node; it changes which data movements software must schedule.
The paper also shows why simple reuse would have failed. A server I/O die carries DDR channels, external links, and topology assumptions that are useful for a socket but waste area and power inside an HBM-centered APU. AMD therefore distributed the base functions across four I/O dies and used short-reach links so that the package behaves as one fabric. Six GPU chiplets and three reused CPU chiplets are hybrid-bonded above those dies, while the HBM stacks sit beside them on an interposer.
Packaging becomes architecture
The integration budget is unusually large: about 146 billion transistors excluding HBM. Hybrid bonding provides dense vertical connections between compute and I/O dies, while 2.5D integration connects the four base dies and eight memory stacks. These technologies decide link energy, reachable bandwidth, repair options, and which chiplets can be reused. In this design, packaging is no longer a back-end implementation detail.
The trade-off is equally physical. A package that removes external data copies concentrates power and heat, increases assembly complexity, and makes known-good-die testing and yield management central to product economics. Unified memory also does not make every workload faster. Applications with little CPU-GPU sharing may benefit less, while workloads whose working set exceeds 128 GB still need a slower external tier.
What we take from it
MI300A demonstrates that heterogeneity becomes most useful when the memory contract is designed with the compute, not when separate devices are merely placed closer together. Its lasting lesson is the sequence of decisions: remove unused server I/O, shorten the fabric, make HBM coherent, and only then stack reusable compute chiplets. Future accelerator packages will be judged by the software-visible boundaries they eliminate, not by chiplet count alone.
Source and attribution
This article is an independent editorial summary written in our own words. No sentences, figures, or tables from the paper are reproduced. The figure was created for this article from reported facts. The public author manuscript states that copyright is held by the authors and publication rights are licensed to ACM; the proceedings version is © 2024 the owner/authors.