Interconnects · Fabrics
08-17[fabric]One DPU, Eight RNICs: Tencent's Pegasus Network for Bare-Metal AI Cloud15m08-10[fabric]Beyond NVLink and Scale-Out Networks: A One-Chip-Like CXL Datacenter33m08-06[fabric]A Flow-Size Distribution Cannot Describe a Burst20m05-04[fabric]Keeping Old NICs on the RDMA Path: What ByteDance's BURST Really Accelerates17m05-04[fabric]A 100K-GPU Network Starts as a Compiler Problem22m05-04[fabric]Compile the Fabric before Deploying It: Meta's Matryoshka Network Design System15m05-04[fabric]Azure Puts Stateful Networking Inside the Switch: The Deployment Logic of SONiC DASH18m04-26[fabric]The Fast Link Is Not the Only Link: MPCCS Stripes GPU Collectives Across Two Fabrics12m02-17[fabric]The 400 µm Modulator That Pushes CPO to 212 Gb/s per Wavelength19m01-30[fabric]Who Wires the Rack: Reading UALink Against NVLink and Ethernet21m
# 2025
10-23[fabric]One RoCE Fabric, Four Distance Classes: Meta's Communication Stack for 100K+ GPUs15m10-12[fabric]Pooling PCIe Devices Without a PCIe Switch14m09-28[fabric]One Photonic Switch, Two Routing Dimensions14m09-08[fabric]An AI Fabric Needs Three Views of the Same Failure19m09-08[fabric]The FLOPS You Cannot Buy, You Wire: Inside Tencent's Half-Million-GPU Fabric20m09-08[fabric]Ask the Switch Which Path the Probe Actually Took18m09-08[fabric]Firing the Switch: A Scale-Up Domain Built from Transceivers19m09-08[fabric]A Local Queue Cannot See the Congestion Two Switches Away18m09-08[fabric]The Training Job Already Knows Which Network Paths Matter18m08-26[fabric]UCIe Crosses the Rack in Light: Ayar Labs' 8.192 Tb/s Optical Retimer15m08-26[fabric]Optics Moves Inside the Silicon: Celestial AI's Photonic Fabric Module15m08-26[fabric]A 4,000 mm² Optical Backplane: Reading Lightmatter's Passage M100016m08-06[fabric]An RDMA NIC Needs a Scheduler, Not Just Faster Queues14m05-28[fabric]CPO Has to Survive Reflow: Intel's Fiber-to-EMIB Package18m05-14[fabric]Pool the Buffer, Not the Device: A CXL Shortcut Around PCIe Switches13m01-30[fabric]Let the Optical Topology Follow the GPU Allocation14m01-23[fabric]Count the Laser: Co-Designing a 224 Gb/s Coherent CPO Link18m# 2024
04-16[fabric]Routable PCIe Is a Fabric, Not a Longer Bus12m04-14[fabric]Spend Delay Before the First Hop to Buy Back Bandwidth21m# 2023
02-07[fabric]The Protocol Debt Inside Hyperscale RoCE14m